公开(公告)号：US20210103345A1

公开(公告)日：2021-04-08

申请号：US17122999

申请日：2020-12-15

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS, INC.

Inventor： Stefano Paolo Rivolta ,  Mahaveer Jain ,  Ashish Bhargava

IPC: G06F3/0346 ,  G06F3/0487

Abstract: Digital signal processing circuitry, in operation, determines, based on accelerometer data, a carry-position of a device. Double-tap detection parameters are set using the determined carry-position. Double-taps are detected using the set double-tap detection parameters. In response to detection of a double-tap, control signals, such as a flag or an interrupt signal, are generated and used to control operation of the device. For example, a device may enter a wake mode of operation in response to detection of a double-tap.

公开(公告)号：US10964551B2

公开(公告)日：2021-03-30

申请号：US15085678

申请日：2016-03-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/321 ,  B24B37/005 ,  H01L21/02 ,  H01L21/66

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

公开(公告)号：US20210089731A1

公开(公告)日：2021-03-25

申请号：US17108646

申请日：2020-12-01

Applicant: STMicroelectronics, Inc.

Inventor： John N. Tran

IPC: G06K7/10 ,  G06K19/07

Abstract: A method includes providing a power supply package (PSP) that includes a power supply, an RFID tag, and a power switch, where a control terminal of the power switch is coupled to an output terminal of the RFID tag, and load path terminals of the power switch are coupled between an output terminal of the PSP and a first terminal of the power supply, where a control register of the RFID tag is pre-programmed with a first value such that the RFID tag is configured to generate a first control signal that turns off the power switch; receiving, by the RFID tag, a second value for the control register of the RFID tag; and writing, by the RFID tag, the second value to the control register of the RFID tag such that the RFID tag is configured to generate a second control signal that turns on the power switch.

公开(公告)号：US10950722B2

公开(公告)日：2021-03-16

申请号：US14588337

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John H. Zhang ,  Carl Radens ,  Lawrence A. Clevenger ,  Yiheng Xu

IPC: H01L29/78 ,  H01L29/165 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238

Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

公开(公告)号：US10943885B2

公开(公告)日：2021-03-09

申请号：US15863079

申请日：2018-01-05

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Talledo

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31

Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.

公开(公告)号：US20210057355A1

公开(公告)日：2021-02-25

申请号：US16996712

申请日：2020-08-18

Applicant: STMicroelectronics, Inc.

Inventor： Ian Harvey ARELLANO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 μm to 5 μm. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

公开(公告)号：US20210050449A1

公开(公告)日：2021-02-18

申请号：US17087218

申请日：2020-11-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10910385B2

公开(公告)日：2021-02-02

申请号：US16510612

申请日：2019-07-12

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/08 ,  H01L27/092 ,  H01L29/739 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  H01L29/49

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

公开(公告)号：US10892281B2

公开(公告)日：2021-01-12

申请号：US16713106

申请日：2019-12-13

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L21/84

Abstract: A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.

公开(公告)号：US20200373416A1

公开(公告)日：2020-11-26

申请号：US16988206

申请日：2020-08-07

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.