公开(公告)号：WO2020074996A1

公开(公告)日：2020-04-16

申请号：PCT/IB2019/058282

申请日：2019-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： KIM, Seyoung ,  KIM, Hyungjun ,  GOKMEN, Tayfun ,  RASCH, Malte

IPC: G06F3/00 ,  G06N3/08 ,  G11C11/00

Abstract: Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array (802, 804) having a set of conductive row wires (806a, 806b) and a set of conductive column wires (808a, 808b) intersecting the set of conductive row wires (806a, 806b), and optimizable crosspoint devices (810a, 810b) at intersections of the set of conductive column wires (808a, 808b) and the set of conductive row wires (806a, 806b). A method for analog array-based vector-matrix computing is also provided that includes: applying repeated voltage pulses to the crosspoint devices (810a) in the weight array until all of the crosspoint devices (810a) in the weight array converge to their own symmetry point; and copying conductance values for each crosspoint devices (810a) from the weight array to the reference array.

公开(公告)号：WO2020074989A1

公开(公告)日：2020-04-16

申请号：PCT/IB2019/058120

申请日：2019-09-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： ARTHUR, John, Vernon ,  CASSIDY, Andrew, Stephen ,  FLICKNER, Myron ,  DATTA, Pallab ,  PENNER, Hartmut ,  APPUSWAMY, Rathinakumar ,  SAWADA, Jun ,  MODHA, Dharmendra ,  ESSER, Steven, Kyle ,  TABA, Brian, Seisho ,  KLAMO, Jennifer

IPC: G06N3/06

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to:receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores,output of one or more neural network layers.

公开(公告)号：WO2020058800A1

公开(公告)日：2020-03-26

申请号：PCT/IB2019/057562

申请日：2019-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： THATHACHAR, Jayram ,  KORNUTA, Tomasz ,  OZCAN, Ahmet, Serkan

IPC: G06N3/04

Abstract: Memory-augmented neural networks are provided. An encoder artificial neural network is adapted to receive an input and provide an encoded output based on the input. A plurality of decoder artificial neural networks is provided, each adapted to receive an encoded input and provide an output based on the encoded input. A memory is operatively coupled to the encoder artificial neural network and to the plurality of decoder artificial neural networks. The memory is adapted to store the encoded output of the encoder artificial neural network and provide the encoded input to the plurality of decoder artificial neural networks.

公开(公告)号：WO2020021400A1

公开(公告)日：2020-01-30

申请号：PCT/IB2019/056138

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： REZNICEK, Alexander ,  ANDO, Takashi ,  HASHEMI, Pouya

IPC: H01L21/336

Abstract: A semiconductor structure includes an oxide Re RAM co-integrated with a drain region of a field effect transistor (FET). The oxide Re RAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide Re RAM and thus helps to control forming of the conductive filament of the oxide Re RAM.

公开(公告)号：WO2020016794A1

公开(公告)日：2020-01-23

申请号：PCT/IB2019/056094

申请日：2019-07-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： FUKUDA, Susumu ,  WATANABE, Kenta ,  ISHIKAWA, Shunsuke ,  FUKUDA, Takashi

IPC: G06F17/27 ,  G06F17/21

Abstract: Embodiments are directed to a system, computer program product, and method for dynamic facet dictionary management. As one or more annotations are applied to a document collection, electronic text and associated facets are identified. Additional facets and facet values are identified and selectively applied to a knowledge base. A dictionary comprised of facets and associated facet values is constructed from the selective application. Application of the dictionary to the knowledge base identifies and returns a targeted document collection. Accordingly, facet mining and dictionary construction are dynamically applied to the knowledge base.

公开(公告)号：WO2020016717A1

公开(公告)日：2020-01-23

申请号：PCT/IB2019/055961

申请日：2019-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： YOSHIZUMI, Takayuki

IPC: G05B13/02

Abstract: A computer-implemented method executed by a robotic system for performing a positional search process in an assembly task is presented. The method includes applying forces to a first component to be inserted into a second component, detecting the forces applied to the first component by employing a plurality of force sensors attached to a robotic arm of the robotic system, extracting training samples corresponding to the forces applied to the first component, normalizing time-series data for each of the training samples by applying a variable transformation about a right tilt direction, creating a time-series prediction model of transformed training data, applying the variable transformation with different directions for a test sample, and calculating a matching ratio between the created time- series prediction model and the transformed test sample.

公开(公告)号：WO2020012399A1

公开(公告)日：2020-01-16

申请号：PCT/IB2019/055912

申请日：2019-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： KARACALI-AKYAMAC, Bengi ,  TRACEY, John, Michael ,  BASSO, Claude ,  CRUMLEY, Paul, Gregory ,  FELTER, Wesley, Michael

IPC: H04L12/26

Abstract: Techniques for network performance assessment are described. Techniques may include collecting initial measurements relating to transmission of probe traffic between endpoints of endpoint pairs in a plurality of endpoint pairs and clustering the plurality of endpoints into a plurality of endpoint groups. The method may also include determining a plurality of endpoint group pairs and generating a network performance assessment, based on measuring performance metrics pertaining to traffic between endpoints within the endpoint groups in the plurality of endpoint group pairs.

公开(公告)号：WO2020008345A1

公开(公告)日：2020-01-09

申请号：PCT/IB2019/055618

申请日：2019-07-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： SOCEANU, Omri ,  GOLDSTEEN, Abigail ,  GREENBERG, Lev ,  ROZENBERG, Boris ,  FARKASH, Ariel

IPC: G06F21/16

Abstract: Embodiments of the present systems and methods may provide data watermarking without reliance on error-tolerant fields, thereby providing for the incorporation of watermarks in data that was not considered suitable for watermarking. For example, in an embodiment, a computer-implemented method for watermarking data may comprise inserting watermark data into a field that requires format-preserving encryption.

公开(公告)号：WO2020003030A1

公开(公告)日：2020-01-02

申请号：PCT/IB2019/054799

申请日：2019-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： TANG, Paul ,  DEVARAKONDA, Murthy

IPC: G16H10/40

Abstract: A mechanism is provided in a data processing system comprising a processor and a memory, the memory comprising instructions that are executed by the processor to specifically configure the processor to implement a cognitive analysis engine for analysis and disambiguation of electronic medical records for presentation of pertinent information for a medical treatment plan. The cognitive analysis engine receives a medical condition for a current or upcoming interaction with a patient. The cognitive analysis engine receives a medical mental model that emulates the thinking of a medical professional with regard to reviewing a patient electronic medical record (EMR) to identify pertinent information for a medical treatment plan to treat the medical condition. The cognitive analysis engine uses the medical mental model to analyze the EMR for the patient to identify at least one portion of the EMR relevant to the medical treatment plan and to analyze the identified at least one portion of the EMR to extract relevant patient information that is directed to the medical treatment plan for the medical condition. The cognitive analysis engine uses the medical mental model to generate and output a cognitive summary correlating the extracted relevant patient information and the medical treatment plan in association with the medical condition.

公开(公告)号：WO2019243962A1

公开(公告)日：2019-12-26

申请号：PCT/IB2019/054954

申请日：2019-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： CASSIDY, Andrew, Stephen ,  APPUSWAMY, Rathinakumar ,  ARTHUR, John, Vernon ,  DATTA, Pallab ,  ESSER, Steven, Kyle ,  FLICKNER, Myron ,  KLAMO, Jennifer ,  MODHA, Dharmendra ,  PENNER, Hartmut ,  SAWADA, Jun ,  TABA, Brian, Seisho

IPC: G06N3/06

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.