公开(公告)号：US20200348137A1

公开(公告)日：2020-11-05

申请号：US16399842

申请日：2019-04-30

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.r.l.

Inventor： Mahaveer JAIN ,  Mahesh CHOWDHARY ,  Roberto MURA ,  Nicola Matteo PALELLA ,  Leonardo COLOMBO

IPC: G01C21/16 ,  G01C21/20 ,  G01S19/49

Abstract: A device including microelectromechanical systems (MEMS) sensors are used in dead reckoning in conditions where Global Positioning System (GPS) signals or Global Navigation Satellite System (GNSS) signals are lost. The device is capable of tracking the location of the device after the GPS/GNSS signals are lost by using MEMS sensors such as accelerometers and gyroscopes. By calculating a misalignment angle between a forward axis of a sensor frame of the device and a forward axis of a vehicle frame using the data received from the MEMS sensors, the device can accurately calculate the location of a user or the vehicle of the device even without the GPS/GNSS signals. Accordingly, a device capable of tracking the location of the user riding in the vehicle in GPS/GNSS signals absent environment can be provided.

公开(公告)号：US10824175B2

公开(公告)日：2020-11-03

申请号：US16044333

申请日：2018-07-24

Applicant: STMicroelectronics, Inc.

Inventor： Dominique Paul Barbier

IPC: G05D7/06 ,  G01F1/50 ,  G05D23/19 ,  G06F1/20

Abstract: Devices, systems, and methods are provided for monitoring air flow through a server using differential pressure measurements. The device includes an external pressure sensor, an internal pressure sensor, and a controller that receives the pressures from the external and internal pressure sensors. The external pressure sensor detects air pressure of the ambient air around a server enclosure, the internal pressure sensor detects air pressure through a server enclosure, and the controller calculates a pressure differential between the pressure from the external pressure sensor and the internal pressure sensor. The controller can then generate a signal based on the pressure differential, the signal optionally controlling a cooling fan, generating an interrupt for the server circuitry, or performing some other action.

公开(公告)号：US10812079B2

公开(公告)日：2020-10-20

申请号：US16142627

申请日：2018-09-26

Applicant: STMicroelectronics, Inc.

Inventor： Chetan Bisht ,  Harry Scrivener, III

IPC: H03K19/0175 ,  H01L23/528 ,  H01L23/50 ,  G06F17/50

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

公开(公告)号：US20200295187A1

公开(公告)日：2020-09-17

申请号：US16886193

申请日：2020-05-28

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10763194B2

公开(公告)日：2020-09-01

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.

公开(公告)号：US20200152765A1

公开(公告)日：2020-05-14

申请号：US16743293

申请日：2020-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： XIUYU CAI ,  CHUN-CHEN YEH ,  QING LIU ,  RUILONG XIE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L21/768 ,  H01L29/417 ,  H01L29/06

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US10649229B2

公开(公告)日：2020-05-12

申请号：US16697028

申请日：2019-11-26

Applicant: STMicroelectronics, Inc.

Inventor： Mark A. Lysinger ,  Chih-Hung Tai ,  James L. Worley ,  Pavan Nallamothu

IPC: G02B27/64 ,  H02P7/025 ,  H04N5/232 ,  G03B5/00 ,  H04N5/225 ,  H02K41/035

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

公开(公告)号：US10649228B2

公开(公告)日：2020-05-12

申请号：US16694749

申请日：2019-11-25

Applicant: STMicroelectronics, Inc.

Inventor： Mark A. Lysinger ,  Pavan Nallamothu ,  Chih-Hung Tai ,  James L. Worley

IPC: G02B27/64 ,  H02K41/035 ,  H02P7/025

Abstract: Various embodiments provide an optical image stabilization circuit including a drive circuit having a power waveform generator and a power waveform conversion circuit. The power waveform generator generates a power waveform. The power waveform conversion circuit converts the power waveform to a power drive signal. An actuator is then driven by the power drive signal to move a lens accordingly and compensate for any movements and vibrations of a housing of the lens.

公开(公告)号：US10600786B2

公开(公告)日：2020-03-24

申请号：US15452049

申请日：2017-03-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Sylvain Maitrejean ,  Emmanuel Augendre ,  Pierre Morin ,  Shay Reboh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/266 ,  H01L21/268 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

公开(公告)号：US10573756B2

公开(公告)日：2020-02-25

申请号：US16228620

申请日：2018-12-20

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/165

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.