公开(公告)号：US08004259B2

公开(公告)日：2011-08-23

申请号：US12256300

申请日：2008-10-22

Applicant: Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

Inventor： Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

IPC: G05F1/40

CPC classification number: H02M3/1588 ,  H02M2001/0012 ,  Y02B70/1466

Abstract: A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

Abstract translation: 提出了一种用于控制功率转换器的系统和方法。 一个实施例包括连接到模拟 - 数字转换器的模拟差分电路，并将数字误差信号与至少第一阈值进行比较。 如果数字误差信号小于第一阈值，则产生脉冲以控制功率转换器。 另一实施例包括可与数字误差信号进行比较的多个阈值。

公开(公告)号：US07990215B2

公开(公告)日：2011-08-02

申请号：US12858310

申请日：2010-08-17

Applicant: Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

Inventor： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

IPC: H03F3/217

CPC classification number: H03F3/2173

Abstract: Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.

Abstract translation: D类放大器的电路和方法。 在一个示例性实施例中，公开了一种音频放大器。 提供用于驱动高侧和低侧驱动晶体管的闭环配置，每个电路与先进的亚微米半导体工艺兼容。 模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。 来自输出的反馈信号也被输入到模数转换器。 位流由模数转换器输出。 抽取器接收该位流，并以较低的频率将样本下变频为数字值。 使用具有适应系数的数字滤波器来对该信号进行滤波，并且数字脉宽调制器然后开发模拟差分PWM信号。 预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。

公开(公告)号：US20090316461A1

公开(公告)日：2009-12-24

申请号：US12546554

申请日：2009-08-24

Applicant: Alan Roth

Inventor： Alan Roth

IPC: G11C15/00 ,  G06F12/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract translation: 一种用于使用可变宽度搜索数据执行搜索操作的内容可寻址存储器（CAM），所述CAM包括多个CAM单元阵列，每个阵列耦合到相应的子搜索数据总线，所述子搜索总线被限制为形成主 搜索数据总线，应用搜索数据; 接收来自相应CAM阵列的匹配线信号的选择器电路，匹配线信号表示在相关联的CAM阵列中形成的搜索和比较的结果，选择器电路响应于选择一个或多个所述匹配的模式选择信号 线路输出信号被切换到优先编码器和多重匹配解算器（PE-MMR），其中在第一模式中，匹配线输出信号被切换到所述PE-MMR，并且在第二模式中，来自所选择的匹配线输出信号组 阵列被切换到所述PE-MMR。

公开(公告)号：US20060152956A1

公开(公告)日：2006-07-13

申请号：US11367507

申请日：2006-03-06

Applicant: Alan Roth

Inventor： Alan Roth

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

公开(公告)号：US5899053A

公开(公告)日：1999-05-04

申请号：US932515

申请日：1997-09-18

Applicant: Scott Alan Roth

Inventor： Scott Alan Roth

IPC: A01D34/73

CPC classification number: A01D34/73

Abstract: A new lawn mower blade for improving the cutting edge to produce a more efficient cutting area. The inventive device includes an elongate blade member, a first scalloped cutting edge region on one end of the blade member, a second scalloped cutting edge region on the other end, a first deflecting fin on the opposite edge of the second scalloped cutting edge region, a second deflecting fin on the opposite edge of the first scalloped cutting edge region, and a mounting means for mounting the blade member to a lawnmower. The new lawn mower blade is designed to increase the surface area of the cutting edge to effectively cut grass cleaner and more even than a conventional rotary lawn mower blade.

Abstract translation: 一种新的割草机刀片，用于改善切割边缘以产生更有效的切割面积。 本发明的装置包括细长叶片构件，在叶片构件的一端上的第一扇形切割边缘区域，在另一端上的第二扇形切割边缘区域，在第二扇形切割边缘区域的相对边缘上的第一偏转翅片， 在第一扇形切割边缘区域的相对边缘上的第二偏转翅片，以及用于将叶片构件安装到割草机的安装装置。 新的割草机叶片设计用于增加切割边缘的表面积，以有效地切割草坪清洁剂，甚至比常规的旋转割草机叶片更均匀。

公开(公告)号：US09479051B2

公开(公告)日：2016-10-25

申请号：US13340746

申请日：2011-12-30

Applicant: Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

Inventor： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

IPC: G05F1/577 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M2001/009

Abstract: A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.

Abstract translation: DC-DC转换器包括开关电路和控制器。 开关电路包括耦合到第一和第二电压供应节点和耦合到多个输出负载的电感器。 控制器被配置为监测通过电感器的电流并且选择性地将电感器耦合到多个输出负载中的每一个，使得满足以下标准中的至少一个：1）通过电感器的平均电流对于特定的 耦合到开关电路的输出负载，或2）在耦合到开关电路的特定输出负载的充电周期期间最小化开关电路切换的次数。

公开(公告)号：US08971004B2

公开(公告)日：2015-03-03

申请号：US13546303

申请日：2012-07-11

Applicant: Alan Roth ,  Eric Soenen

Inventor： Alan Roth ,  Eric Soenen

IPC: H02H5/04

CPC classification number: G05B11/01 ,  G01K7/16 ,  G01K15/005 ,  G05B15/02 ,  H03M3/344 ,  H03M3/458

Abstract: A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery powered devices and includes a processor that analyzes a measured temperature signal and decides if the thermal sensor operates in low or high power operational mode, or if the device's CPU is to be reset. A method utilizing the thermal sensor includes making comparisons to two threshold temperatures and operating at low power mode below the first threshold temperature, high power mode between the two threshold temperatures and causing reset if the second threshold temperature is exceeded. Low power operational mode includes a lower clock frequency, lower bias current and lower power consumption. Higher power operational mode is used when the upper threshold temperature is being approached and includes a higher data sampling frequency and more accurate temperature control and uses higher power.

Abstract translation: 高精度片上热传感器包括集成电路和感测元件。 热传感器可用于各种移动和电池供电的设备，并包括一个处理器，用于分析测量的温度信号，并决定热传感器是在低功耗还是高功率运行模式下运行，或者设备的CPU是否被复位。 利用热传感器的方法包括比较两个阈值温度并在低于第一阈值温度的低功率模式下工作，在两个阈值温度之间的高功率模式，并且如果超过第二阈值温度则引起复位。 低功耗操作模式包括较低的时钟频率，较低的偏置电流和较低的功耗。 当接近上限阈值时使用更高功率的工作模式，并且包括更高的数据采样频率和更准确的温度控制，并且使用更高的功率。

公开(公告)号：US08324955B2

公开(公告)日：2012-12-04

申请号：US13051343

申请日：2011-03-18

Applicant: Alan Roth ,  Ying-Chih Hsu ,  Justin Shi ,  Eric Soenen

Inventor： Alan Roth ,  Ying-Chih Hsu ,  Justin Shi ,  Eric Soenen

IPC: H03L5/00

CPC classification number: H03K19/018507 ,  H03K3/037

Abstract: A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

Abstract translation: 电平移位器接收输入电压信号并产生输出电压信号。 电平移位器包括第一反相器，其被配置为在第一电压V1和第二电压V2之间的电位差下工作。 反相器的输出通过电容电容耦合到锁存电路的输入端。 电容器具有连接到第一反相器的输出端子的第一端子，并且还具有第二端子。 电平移位器具有连接到第三电压V3的电阻器和用于将输入端连接到锁存电路的电容器以达到期望的电压。 闩锁电路被配置为在第四电压V4和第五电压V5之间的电位差下工作。 锁存器具有连接到电阻器和电容器的输入节点，并且还具有连接到电平移位器的输出节点的输出节点。

公开(公告)号：USRE43552E1

公开(公告)日：2012-07-24

申请号：US12709198

申请日：2010-02-19

Applicant: Alan Roth ,  Sean Lord ,  Robert McKenzie ,  Dieter Haerle ,  Steven Smith

Inventor： Alan Roth ,  Sean Lord ,  Robert McKenzie ,  Dieter Haerle ,  Steven Smith

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract translation: 一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址 在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块 具有最高优先级的数据输入。

公开(公告)号：US08069363B2

公开(公告)日：2011-11-29

申请号：US12543839

申请日：2009-08-19

Applicant: Alan Roth ,  Oswald Becca ,  Pedro Ovalle

Inventor： Alan Roth ,  Oswald Becca ,  Pedro Ovalle

IPC: G06F1/12 ,  H03L7/00

CPC classification number: G06F5/08

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract translation: 提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。 第一透明锁存器接收与输入时钟同步的数据。 第二透明锁存器从第一透明锁存器接收数据，并且输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。 输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。