中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

128 records (took 0.02 seconds)

    Circuit for limiting the maximum current supplied to a load by a power transistor
    21.
    发明公开
    Circuit for limiting the maximum current supplied to a load by a power transistor 失效
    Schaltung zur Begrenzung des Maximalstroms，den ein Leistungstransistor an eine Last liefert。

    公开(公告)号：EP0639894A1

    公开(公告)日：1995-02-22

    申请号：EP93830354.2

    申请日：1993-08-18

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Aiello, Natale ,  Palara, Sergio ,  Scaccianoce, Salvatore

    IPC: H03K17/08 ,  H03K17/16

    CPC classification number: H03K17/08126 ,  H03K17/0826 ,  H03K17/16

    Abstract: A limiter circuit for the maximum current passed from a power transistor (T'p) to a load (ZL) connected to an output terminal of the transistor, being of a type which comprises an error amplifier (1'), a driver circuit (P') for said transistor (T'p), and a means of detecting the current (IL) flowing through said load (ZL) provided with at least first and second terminals, is characterized in that it comprises a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal of the amplifier (1'), one input (B') of said amplifier (1') being connected to said first terminal of (Rs)and the other input (A') connected to said second terminal of (Rs). The introduction of said circuit block lowers the open-ring system gain making it stable and producing a smooth reduction of any rise in the load current (IL).

    Abstract translation: 用于从功率晶体管（T'p）到连接到晶体管的输出端子的负载（ZL）的最大电流的限幅器电路，其包括误差放大器（1'），驱动器电路 P'），以及检测流过设置有至少第一和第二端子的所述负载（ZL）的电流（IL）的装置，其特征在于，其包括电路块（2） 具有连接到（T'p）的控制端的输入端和连接到放大器（1'）的电流发生器内部的输出端，所述放大器（1'）的一个输入（B'）连接到所述 （Rs）的第一端子和连接到（Rs）的所述第二端子的另一输入端（A'）。 所述电路块的引入降低了开环系统增益，使其稳定，并且可以平滑地减少负载电流（IL）的任何上升。

    A vertical bipolar power transistor with buried base and interdigitated geometry
    22.
    发明公开
    A vertical bipolar power transistor with buried base and interdigitated geometry 失效
    Vertikaler Bipolar-Leistungstransistor mit vergrabener Basis und ineinandergreifender Geometrie。

    公开(公告)号：EP0632505A1

    公开(公告)日：1995-01-04

    申请号：EP93830287.4

    申请日：1993-07-01

    Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    Inventor： Palara, Sergio

    IPC: H01L29/73 ,  H01L29/08

    CPC classification number: H01L29/0804 ,  H01L29/7304

    Abstract: The transistor comprises a buried base P region (13), a buried emitter N+ region (14) with elongate portions (fingers), deep contact P+ base regions (15), emitter N+ interconnection regions (16,17) serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" (14) there are associated a screening P region (22) interposed between the "finger" (14) and a part (16) of the respective N+ interconnection region, and a contact N+ region (17A) which extends to the "finger" and is surface connected to the screening P region (22) by a dedicated electrode (23).

    Abstract translation: 晶体管包括掩埋基极P区域（13），具有细长部分（指状物），深触点P +基极区域（15），用于平衡电阻器功能的发射极N +互连区域（16,17）的掩埋发射极N +区域（14） 和基极，发射极和集电极表面接触电极。 为了提供更高的电流增益和更大的安全操作区域，对于每个发射器“手指”（14），存在插入在“手指”（14）和相应的“手指”（14）的部分（16）之间的屏蔽P区域（22） N +互连区域和延伸到“手指”并且通过专用电极（23）表面连接到屏蔽P区域（22）的触点N +区域（17A）。

Patent Agency Ranking