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    INSULATED GATE BIPOLAR TRANSISTOR (IGBT) AND METHOD FOR MANUFACTURING THE SAME
    22.
    发明申请
    INSULATED GATE BIPOLAR TRANSISTOR (IGBT) AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    绝缘栅双极晶体管（IGBT）及其制造方法

    公开(公告)号：WO2012075905A1

    公开(公告)日：2012-06-14

    申请号：PCT/CN2011/083300

    申请日：2011-12-01

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Le

    Inventor： WANG, Le

    IPC: H01L29/72 ,  H01L29/735

    CPC classification number: H01L29/7393 ,  H01L29/66325

    Abstract: An insulated gate bipolar transistor (IGBT) is disclosed. The IGBT includes a substrate containing a substrate layer and an epitaxial layer formed on one side of the substrate layer. The IGBT also includes a well region formed in the epitaxial layer, and a gate region formed over a junction between the well region and the epitaxial layer. Further, the IGBT includes a collector drift region formed in the epitaxial layer, and an emitter drift region formed in the well region. The IGBT also includes a collector formed on the collector drift region, an emitter formed on the emitter drift region, and a gate formed on the gate region. The collector, the emitter, and the gate are arranged at a same side of the substrate layer.

    Abstract translation: 公开了一种绝缘栅双极晶体管（IGBT）。 IGBT包括含有衬底层和形成在衬底层的一侧上的外延层的衬底。 IGBT还包括形成在外延层中的阱区和形成在阱区和外延层之间的结上方的栅极区。 此外，IGBT包括形成在外延层中的集电极漂移区和形成在阱区中的发射极漂移区。 IGBT还包括形成在集电极漂移区上的集电极，形成在发射极漂移区上的发射极和形成在栅极区上的栅极。 集电极，发射极和栅极配置在基板层的同一侧。

    METHOD FOR MANUFACTURING METAL-OXIDE-SEMICONDUCT OR FIELD-EFFECT TRANSISTORS
    23.
    发明申请
    METHOD FOR MANUFACTURING METAL-OXIDE-SEMICONDUCT OR FIELD-EFFECT TRANSISTORS 审中-公开
    制造金属氧化物半导体或场效应晶体管的方法

    公开(公告)号：WO2012071990A1

    公开(公告)日：2012-06-07

    申请号：PCT/CN2011/082419

    申请日：2011-11-18

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  ALIYEU, Alihajy

    Inventor： ALIYEU, Alihajy

    IPC: H01L21/336

    CPC classification number: H01L21/26513 ,  H01L21/28035 ,  H01L29/66681

    Abstract: A method is disclosed for manufacturing a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The method includes providing a substrate containing an epitaxial layer, forming a gate oxide layer and a polysilicon layer on the epitaxial layer, and forming a photoresist layer on the polysilicon layer and a gate region pattern in the photoresist layer. The method also includes forming a gate region by etching the polysilicon layer using the gate region pattern in the photoresist layer as a mask. The etching is performed in such a way that the gate region has a lateral surface receding at a predetermined length relative to the gate region pattern in the photoresist layer. Further, the method includes forming a body region by ion implantation and dopant drive-in using the photoresist layer as a mask such that an overlapping area between the body region and the gate region can be reduced based on the predetermined receding length.

    Abstract translation: 公开了用于制造金属氧化物半导体场效应晶体管（MOSFET）的方法。 该方法包括提供包含外延层的衬底，在外延层上形成栅极氧化层和多晶硅层，以及在多晶硅层上形成光致抗蚀剂层和在光刻胶层中形成栅极区域图案。 该方法还包括通过使用光致抗蚀剂层中的栅极区域图案作为掩模蚀刻多晶硅层来形成栅极区域。 以这样的方式进行蚀刻，使得栅极区域相对于光致抗蚀剂层中的栅极区域图案具有以预定长度退出的侧表面。 此外，该方法包括通过使用光致抗蚀剂层作为掩模的离子注入和掺杂剂驱入形成体区域，使得能够基于预定的后退长度来减小体区域和栅极区域之间的重叠区域。

    METHOD FOR MANUFACTURING DUAL-GATE OXIDE SEMICONDUCTOR DEVICES
    24.
    发明申请
    METHOD FOR MANUFACTURING DUAL-GATE OXIDE SEMICONDUCTOR DEVICES 审中-公开
    用于制造双栅氧化物半导体器件的方法

    公开(公告)号：WO2012071986A1

    公开(公告)日：2012-06-07

    申请号：PCT/CN2011/082395

    申请日：2011-11-18

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Le

    Inventor： WANG, Le

    IPC: H01L21/8234 ,  H01L21/31 ,  H01L21/266 ,  H01L29/78

    CPC classification number: H01L21/823857 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/28211 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/32105 ,  H01L21/76202 ,  H01L21/823462

    Abstract: A method is provided for manufacturing a dual-gate oxide semiconductor device. The method includes providing a substrate including a first gate oxide layer region and a second gate oxide layer region, and forming a photoresist pattern of the second gate oxide layer region on a surface of the substrate (S101). The method also includes implanting nitrogen atoms into the first gate oxide layer region by an ion implantation process using the photoresist pattern of the second gate oxide layer region as a mask to form a nitrogen implantation layer (S102). Further, the method includes removing the photoresist pattern on the surface of the substrate to expose the second gate oxide layer region (S103), and forming a first gate oxide layer and a second gate oxide layer on the surface of the substrate at the same time by a single thermal oxidation process (S104). Furthermore, the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness, which is different from the first thickness.

    Abstract translation: 提供了制造双栅极氧化物半导体器件的方法。 该方法包括提供包括第一栅极氧化物层区域和第二栅极氧化物层区域的衬底，以及在衬底的表面上形成第二栅极氧化物层区域的光致抗蚀剂图案（S101）。 该方法还包括通过使用第二栅极氧化物层区域的光致抗蚀剂图案作为掩模的离子注入工艺将氮原子注入到第一栅极氧化物层区域中以形成氮注入层（S102）。 此外，该方法包括去除衬底的表面上的光致抗蚀剂图案以暴露第二栅极氧化物层区域（S103），并且同时在衬底的表面上形成第一栅极氧化物层和第二栅极氧化物层 通过单次热氧化处理（S104）。 此外，第一栅极氧化物层具有第一厚度，并且第二栅极氧化物层具有与第一厚度不同的第二厚度。

    LDMOS DEVICE AND METHOD FOR FABRICATING THE SAME
    25.
    发明申请
    LDMOS DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    LDMOS器件及其制造方法

    公开(公告)号：WO2012065514A1

    公开(公告)日：2012-05-24

    申请号：PCT/CN2011/081730

    申请日：2011-11-03

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Le

    Inventor： WANG, Le

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368

    Abstract: The LDMOS device includes: a substrate including an epitaxial layer and a well region located in the epitaxial layer; a source region in the well region, and a drain region in the epitaxial layer; a first region and a second region in the surface of the epitaxial layer and having doping states different from a doping state of the epitaxial layer, where the first region and the second region are in a drift region between the source region and the drain region, and have different doping states; a field oxide layer above the first region and the second region; and a gate region on the well region and the field oxide layer. The doping states of the first region and the second region may be adapted to simultaneously raise breakdown voltage and lower on-resistance to reduce power consumption of the device.

    Abstract translation: LDMOS器件包括：衬底，其包括外延层和位于外延层中的阱区; 阱区中的源极区和外延层中的漏极区; 在所述外延层的表面中的第一区域和第二区域，并且具有与所述外延层的掺杂状态不同的掺杂态，其中所述第一区域和所述第二区域处于所述源极区域和所述漏极区域之间的漂移区域中， 并具有不同的掺杂态; 在所述第一区域和所述第二区域上方的场氧化物层; 以及阱区和场氧化物层上的栅极区。 第一区域和第二区域的掺杂状态可以适于同时提高击穿电压和降低导通电阻以降低器件的功耗。

    HIGH-VOLTAGE MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME
    26.
    发明申请
    HIGH-VOLTAGE MOS DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    高电压MOS器件及其制造方法

    公开(公告)号：WO2012034515A1

    公开(公告)日：2012-03-22

    申请号：PCT/CN2011/079616

    申请日：2011-09-14

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  ZHAO, Zhiyong ,  WANG, Le ,  GUI, Linchun ,  ZHU, Kongwei

    Inventor： ZHAO, Zhiyong ,  WANG, Le ,  GUI, Linchun ,  ZHU, Kongwei

    IPC: H01L29/78

    CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66734

    Abstract: A high-voltage MOS device comprising a substrate, which includes a body layer and an epitaxial layer formed on the body layer and being of a first conductivity type. The device also includes a first and a second regions located in the epitaxial layer. The first and second regions have a same doping state, and are of a second conductivity type. The device further includes a gate oxide layer formed on an inner surface of a trench located in the epitaxial layer and between the first and second regions and a gate formed on the gate oxide layer. A bottom of the trench extends into the body layer. The device also includes a first and a second body regions located at sides of the trench, and having a same doping state. The device also includes a first and a second source regions located in the first and second body regions, respectively. The first and second source regions have a same doping state, and are of the first conductivity type.

    Abstract translation: 一种高压MOS器件，包括衬底，其包括主体层和形成在所述主体层上并且是第一导电类型的外延层。 该器件还包括位于外延层中的第一和第二区域。 第一和第二区域具有相同的掺杂状态，并且是第二导电类型。 该器件还包括形成在位于外延层中并位于第一和第二区域之间的沟槽的内表面上的栅极氧化物层和形成在栅极氧化物层上的栅极。 沟槽的底部延伸到体层。 该器件还包括位于沟槽侧面的第一和第二体区，并具有相同的掺杂状态。 该装置还包括分别位于第一和第二身体区域中的第一和第二源区域。 第一和第二源区具有相同的掺杂状态，并且是第一导电类型。

    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    28.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件结构及其制造方法

    公开(公告)号：WO2011044833A1

    公开(公告)日：2011-04-21

    申请号：PCT/CN2010/077670

    申请日：2010-10-12

    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  XIE, Baoqiang ,  ZHU, Xuan ,  XIAO, Yujie ,  YANG, Zhaoyu

    Inventor： XIE, Baoqiang ,  ZHU, Xuan ,  XIAO, Yujie ,  YANG, Zhaoyu

    IPC: H01L23/52 ,  H01L23/522

    CPC classification number: H01L23/52 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a semiconductor substrate having a device area and a virtual area, the virtual area being located at an edge of the semiconductor substrate; a first conductive plug and a second conductive plug, wherein the first conductive plug is provided in the virtual area and electrically connected to the substrate; a metal layer disposed in contact with the first and second plugs to provide a conductive path; wherein the first conductive plug, the second conductive plug, and metal layer form an interconnection line structure electrically grounded through a portion of the substrate in the virtual area via the first conductive plug.

    Abstract translation: 提供半导体器件结构及其制造方法。 半导体器件结构包括具有器件区域和虚拟区域的半导体衬底，虚拟区域位于半导体衬底的边缘处; 第一导电插塞和第二导电插头，其中所述第一导电插头设置在所述虚拟区域中并电连接到所述基板; 设置成与所述第一和第二插头接触以提供导电路径的金属层; 其中所述第一导电插塞，所述第二导电插头和金属层形成经由所述第一导电插塞通过所述虚拟区域中的所述基板的一部分电接地的互连线结构。

    絶縁ゲートバイポーラトランジスタおよびその製造方法
    29.
    发明专利
    絶縁ゲートバイポーラトランジスタおよびその製造方法 有权

    公开(公告)号：JP2021506111A

    公开(公告)日：2021-02-18

    申请号：JP2020530373

    申请日：2018-11-27

    Applicant: 無錫華潤上華科技有限公司 ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： 羅 澤煌

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/739

    Abstract: 基板(10)と、下向きに延在するトレンチが表面に設けられた第1の導電型ベース(20)と、第1の導電型ベース(20)内において、トレンチの両側に設けられたコレクタドーピング領域(26)と、第2の導電型ベース(22)と、トレンチの内面に設けられたゲート酸化層(32)と、ゲート酸化層(32)の内側に位置し、トレンチの底部および側壁の一部の領域に充填される多結晶シリコンゲート(40)と、第2の導電型ベース(22)内で、多結晶シリコンゲート(40)の間においてトレンチの下部に設けられたエミッタドーピング領域(24)と、トレンチの上方から下向きに延在し、エミッタドーピング領域(24)を貫通してから、第2の導電型ベース(22)と接触する導電プラグ(50)と、トレンチ内において、導電プラグ(50)と多結晶シリコンゲート(40)との間に充填される絶縁酸化層(34)と、を含むIGBTおよびその製造方法。

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