中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

1795 records (took 0.039 seconds)

    PROCESS FOR LOCALIZED REPAIR OF GRAPHENE-COATED LAMINATION STACKS AND PRINTED CIRCUIT BOARDS
    21.
    发明申请
    PROCESS FOR LOCALIZED REPAIR OF GRAPHENE-COATED LAMINATION STACKS AND PRINTED CIRCUIT BOARDS 审中-公开

    公开(公告)号：WO2022243894A1

    公开(公告)日：2022-11-24

    申请号：PCT/IB2022/054618

    申请日：2022-05-18

    Applicant: MELLANOX TECHNOLOGIES, LTD. ,  BAR-ILAN UNIVERSITY

    Inventor： NAVEH, Doron ,  SMOLINSKY, Eilam Zigi Ben ,  LEVI, Adi ,  MENTOVICH, Elad ,  ATIAS, Boaz

    IPC: C23C16/04 ,  G03F7/16 ,  G03F7/20 ,  H01L21/285

    Abstract: Processes for localized lasering of a lamination stack and graphene-coated printed circuit board (PCB) are disclosed. An example PCB may include a lamination stack, post-lamination, that may further include a core, an adhesive layer, and at least one graphene-metal structure. A top layer of graphene of the graphene-metal structure may have never been grown before the lamination process or may have been removed post-lamination such that a portion of the top layer of graphene is missing. The localized lasering process described herein may grow (for the first time) or re-grow the graphene layer of the exposed portion of the metal layer without adverse effects to the rest of the lamination stack or PCB and while promoting a uniform layer of graphene on the top surface. A process of growing graphene through application of molecular layer and a self-assembled monolayer (SAM), are also described herein.

    ZERO-COPY BUFFERING OF TRAFFIC OF LONG-HAUL LINKS
    24.
    发明申请
    ZERO-COPY BUFFERING OF TRAFFIC OF LONG-HAUL LINKS 审中-公开

    公开(公告)号：WO2022172091A1

    公开(公告)日：2022-08-18

    申请号：PCT/IB2022/050034

    申请日：2022-01-04

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： MULA, Liron ,  MATARI, Idan ,  AIBESTER, Niv ,  ELIAS, George ,  LEVI, Lion

    IPC: H04L49/9005 ,  H04L47/283 ,  H04L67/568

    Abstract: A network device (100) includes multiple ports (102, 104), multiple buffer slices (106), a controller (101), and buffer control circuitry (112, 114). The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

    VOLTAGE CONTROLLED ELECTRO-OPTICAL SERIALIZER/DESERIALIZER (SERDES)
    25.
    发明申请
    VOLTAGE CONTROLLED ELECTRO-OPTICAL SERIALIZER/DESERIALIZER (SERDES) 审中-公开

    公开(公告)号：WO2021094790A1

    公开(公告)日：2021-05-20

    申请号：PCT/GR2019/000080

    申请日：2019-11-14

    Applicant: MELLANOX TECHNOLOGIES LTD ,  KALAVROUZIOTIS, Dimitrios

    Inventor： ARGYRIS, Nikos ,  ROZENBERG, Yoav ,  MENTOVICH, Elad

    IPC: H04B10/50 ,  H04B10/564

    Abstract: An optoelectronic transmitter (10) includes an electro-optic modulator (12), digital driving circuitry (14), and feedback circuitry (30). The electro-optic modulator is configured to modulate an optical signal in response to an electrical drive signal. The digital driving circuitry is coupled to the electro-optical modulator and is configured to generate the electrical drive signal. The feedback circuitry is configured to measure a quantity indicative of a power level of the modulated optical signal produced by the electro-optic modulator, and to adapt a supply voltage to the digital driving circuitry in response to the measured quantity.

    DYNAMIC BANDWIDTH CONNECTIONS
    26.
    发明申请
    DYNAMIC BANDWIDTH CONNECTIONS 审中-公开

    公开(公告)号：WO2021032999A1

    公开(公告)日：2021-02-25

    申请号：PCT/GR2019/000057

    申请日：2019-08-21

    Applicant: MELLANOX TECHNOLOGIES LTD. ,  BAKOPOULOS, Paraskevas ,  KALAVROUZIOTIS, Dimitrios

    Inventor： LEVI, Dotan ,  MENTOVICH, Elad ,  RAVID, Ran ,  SHAPIRO, Roee ,  GANOR, Avraham

    IPC: G06F13/40

    Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

    積體電路電感器
    28.
    发明专利
    積體電路電感器 审中-公开
    集成电路电感器

    公开(公告)号：TW201444054A

    公开(公告)日：2014-11-16

    申请号：TW103105950

    申请日：2014-02-21

    Applicant: 梅爾那斯科技有限公司 ,  MELLANOX TECHNOLOGIES LTD.

    Inventor： 斯摩利 尤西 ,  SMELOY, YOSSI ,  佛斯特 艾爾 ,  FROST, EYAL

    IPC: H01L27/04

    CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: 本發明揭示一種形成於包含交替導電及絕緣層之一電路結構中之電感裝置。該裝置在複數個該等導電層中包含該複數個該等導電層中之每一者中之形成一各別交錯環路對之跡線及至少一個互連分段。在該複數個該等導電層當中之每一層中，該各別對中之至少一個環路藉由至形成於該層上方或下方之另一層中之一互連分段之跨接件閉合。

    Abstract in simplified Chinese: 本发明揭示一种形成于包含交替导电及绝缘层之一电路结构中之电感设备。该设备在复数个该等导电层中包含该复数个该等导电层中之每一者中之形成一各别交错环路对之迹线及至少一个互连分段。在该复数个该等导电层当中之每一层中，该各别对中之至少一个环路借由至形成于该层上方或下方之另一层中之一互连分段之跨接件闭合。

Patent Agency Ranking