公开(公告)号：US06727995B1

公开(公告)日：2004-04-27

申请号：US09903884

申请日：2001-07-12

Applicant: Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

Inventor： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC: G01B1106

CPC classification number: H01L21/28194 ,  G01B11/0625 ,  H01L21/67253 ,  H01L29/517 ,  H01L29/518

Abstract: A system for regulating gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more gate oxide layers being deposited and/or formed on a wafer. Light reflected from the gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective gate oxide layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective gate oxide layers on the wafer. The system also includes a plurality of gate oxide layer formers where each gate oxide former corresponds to a respective portion of the wafer and provides for gate oxide layer formation thereon. The processor selectively controls the gate oxide layer formers to regulate gate oxide layer formation on the respective gate oxide layer formations on the wafer.

Abstract translation: 提供了一种用于调节栅氧化层形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个栅极氧化物层。 从栅极氧化层反射的光被测量系统收集，该系统处理所收集的光。 所收集的光表示晶片上各个栅极氧化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上各个栅极氧化物层的厚度和/或均匀性。 该系统还包括多个栅极氧化物层形成器，其中每个栅极氧化物形成体对应于晶片的相应部分并且在其上形成栅极氧化物层。 处理器选择性地控制栅极氧化物层形成器以调节在晶片上的各个栅极氧化物层形成上的栅极氧化物层形成。

公开(公告)号：US06689541B1

公开(公告)日：2004-02-10

申请号：US09884182

申请日：2001-06-19

Applicant: Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

Inventor： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

IPC: G03C500

CPC classification number: G03F7/38 ,  G03F7/265 ,  G03F7/40

Abstract: In a process for forming a photoresist mask, a photoresist layer is applied to a substrate. A silyated layer is formed in the photoresist layer. The features of the silyated area correspond to the features of a photoresist mask to be formed. The photoresist layer is then etched to form a photoresist base beneath the silyated area. The photoresist base is etched to remove material from its sides such that it becomes narrower than the silyated area. The silyated area is then removed, leaving a photoresist mask on the substrate.

Abstract translation: 在形成光致抗蚀剂掩模的工艺中，将光致抗蚀剂层施加到基底上。 在光致抗蚀剂层中形成硅化层。 硅酸盐化区域的特征对应于要形成的光致抗蚀剂掩模的特征。 然后蚀刻光致抗蚀剂层以在硅化区域下方形成光致抗蚀剂基底。 蚀刻光致抗蚀剂基底以从其侧面去除材料，使得它比斯里芬特区域变窄。 然后除去硅酸盐化区域，在基材上留下光刻胶掩模。

公开(公告)号：US06685467B1

公开(公告)日：2004-02-03

申请号：US09709827

申请日：2000-11-10

Applicant: Ramkumar Subramanian

Inventor： Ramkumar Subramanian

IPC: F27D500

CPC classification number: H01L21/67248 ,  F27B17/0025 ,  H01L21/67109

Abstract: The invention provides systems and methods for controlling resist baking processes, such as PEB of chemically amplified photoresists. A system of the invention provides a baking plate through which hot fluids and cold fluids may be alternately circulated. The system takes measurements relating to temperature of the baking plate, temperature of the resist, and/or extent of the baking process. Using this data, the system controls the baking temperature and/or the overall extent of the baking process through control over the flow of hot and cold fluids. By alternating between hot and cold fluid circulation, systems of the invention provide rapidly responsive temperature control and/or abrupt termination of baking. Control over the baking process is further increased by implementing flow and process control separately over each of a plurality of different portions of a baking plate.

Abstract translation: 本发明提供了用于控制抗蚀剂烘烤过程的系统和方法，例如化学放大光致抗蚀剂的PEB。 本发明的系统提供一种烘烤板，热流体和冷流体可以通过该烘烤板交替循环。 该系统测量与烘烤板的温度，抗蚀剂的温度和/或烘烤过程的程度有关的测量。 使用这些数据，该系统通过控制热和冷流体的流动来控制烘烤温度和/或烘烤过程的总体程度。 通过在热和冷流体循环之间交替，本发明的系统提供快速响应的温度控制和/或突然终止烘烤。 通过在烘烤板的多个不同部分中的每一个上分别实施流程和过程控制来进一步提高烘烤过程的控制。

公开(公告)号：US06656763B1

公开(公告)日：2003-12-02

申请号：US10385375

申请日：2003-03-10

Applicant: Jane V. Oglesby ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Angela T. Hui ,  Minh Van Ngo ,  Suzette K. Pangrle

Inventor： Jane V. Oglesby ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Angela T. Hui ,  Minh Van Ngo ,  Suzette K. Pangrle

IPC: H01L5140

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/16 ,  G11C2213/71 ,  H01L27/285 ,  H01L51/0003 ,  H01L51/0004 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/005 ,  H01L51/0053 ,  H01L51/0059 ,  H01L51/0062 ,  H01L51/0077 ,  H01L51/0078 ,  H01L51/0081 ,  H01L51/0084 ,  H01L51/0085 ,  Y10S977/843 ,  Y10S977/944

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.

Abstract translation: 公开了一种在两个电极之间制造具有可控导电介质的两个电极制成的有机存储单元的方法。 可控导电介质包含有机半导体层和无源层。 在某些溶剂的帮助下，使用旋转技术形成有机半导体层。

公开(公告)号：US06605546B1

公开(公告)日：2003-08-12

申请号：US09901699

申请日：2001-07-11

Applicant: Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

Inventor： Ramkumar Subramanian ,  Wolfram Grundke ,  Bhanwar Singh ,  Christopher F. Lyons ,  Marina V. Plat

IPC: H01L21302

CPC classification number: H01L21/76808

Abstract: A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

Abstract translation: 一种用于形成半导体器件的方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 执行第一次加热以将BARC层加热至流动温度。 执行第二次加热以将BARC层加热至硬化温度，使得BARC层硬化，其中硬化温度大于流动温度。 进行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的硬化的BARC层在蚀刻期间用作耐蚀刻层。 作为第二加热步骤的替代方案，BARC可以简单地硬化。 第一和第二加热可以在加热室内进行，而不去除半导体衬底。

公开(公告)号：US06589804B1

公开(公告)日：2003-07-08

申请号：US09904089

申请日：2001-07-12

Applicant: Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

Inventor： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC: H01L2100

CPC classification number: G01B11/0625

Abstract: A system for regulating ON and/or ONO dielectric formation is provided. The system includes one or more light sources, each light source directing light to one or more oxide and/or nitride layers being deposited and/or formed on a wafer. Light reflected from the oxide and/or nitride layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The measuring system provides thickness and/or uniformity related data to a processor that determines the thickness and/or uniformity of the respective oxide and/or nitride layers on the wafer. The system also includes a plurality of oxide/nitride formers; each oxide/nitride former corresponding to a respective portion of the wafer and providing for ON and/or ONO formation thereon. The processor selectively controls the oxide/nitride formers to regulate oxide and/or nitride layer formation on the respective ON and/or ONO formations on the wafer.

Abstract translation: 提供了一种用于调节ON和/或ONO电介质形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氧化物和/或氮化物层。 从氧化物和/或氮化物层反射的光被测量系统收集，该系统处理收集的光。 所收集的光指示晶片上各个氧化物和/或氮化物层的厚度和/或均匀性。 测量系统向处理器提供厚度和/或均匀性相关数据，其确定晶片上相应氧化物和/或氮化物层的厚度和/或均匀性。 该系统还包括多个氧化物/氮化物成形器; 每个氧化物/氮化物成形器对应于晶片的相应部分并且在其上提供ON和/或ONO形成。 处理器选择性地控制氧化物/氮化物成形器以调节晶片上相应的ON和/或ONO形成上的氧化物和/或氮化物层的形成。

公开(公告)号：US06563221B1

公开(公告)日：2003-05-13

申请号：US10081982

申请日：2002-02-21

Applicant: Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

Inventor： Scott A. Bell ,  Todd P. Lukanc ,  Christopher F. Lyons ,  Marina V. Plat ,  Ramkumar Subramanian

IPC: H01L2348

CPC classification number: H01L21/76885 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method for forming a connection structure in an integrated circuit, a first conducting material is deposited over a substrate and patterned to form a conducting stud in electrical contact with a conducting element of the substrate. A dielectric is formed over the substrate and the conducting stud. A trench is formed in the dielectric to expose a top portion of the conducting stud, and a second conducting material is inlaid in the trench to form wiring in electrical contact with the conducting stud. The electrically conducting element of the substrate may be an element of a semiconductor device or a wiring, contact or via. The first conducting material may be aluminum, and the second conducting material may be copper. The dielectric may be formed as a single layer and may be an organic low-k dielectric. Related connection structures are also disclosed.

Abstract translation: 在用于在集成电路中形成连接结构的方法中，第一导电材料沉积在衬底上并被图案化以形成与衬底的导电元件电接触的导电柱。 电介质形成在衬底和导电柱上。 在电介质中形成沟槽以暴露导电柱的顶部，并且第二导电材料镶嵌在沟槽中以形成与导电柱电接触的布线。 衬底的导电元件可以是半导体器件或布线，接触或通孔的元件。 第一导电材料可以是铝，第二导电材料可以是铜。 电介质可以形成为单层，并且可以是有机低k电介质。 还公开了相关的连接结构。

公开(公告)号：US06562248B1

公开(公告)日：2003-05-13

申请号：US09817518

申请日：2001-03-26

Applicant: Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

Inventor： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

IPC: G01N2100

CPC classification number: G03F1/84 ,  G03F1/26

Abstract: A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.

Abstract translation: 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源，每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集，该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。

公开(公告)号：US06562185B2

公开(公告)日：2003-05-13

申请号：US09955552

申请日：2001-09-18

Applicant: Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

Inventor： Steven C. Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Ramkumar Subramanian

IPC: B24B3700

CPC classification number: B24B37/015

Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.

Abstract translation: 提供了表征化学机械抛光工艺的系统。 该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。 该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。 这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。 这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。 可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备 。

公开(公告)号：US06534418B1

公开(公告)日：2003-03-18

申请号：US09845656

申请日：2001-04-30

Applicant: Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

Inventor： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC: H01L21302

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/7833

Abstract: An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

Abstract translation: 使用含硅成像层来限定次分辨率门结构的示例性方法可以包括在多晶硅层上沉积抗反射涂层，在抗反射涂层上沉积成像层，选择性地蚀刻抗反射涂层以形成 使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。 因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用修剪蚀刻技术，而不会有抗蚀剂侵蚀或高宽比图案崩溃的风险。 这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。