公开(公告)号：WO2012027625A9

公开(公告)日：2012-03-01

申请号：PCT/US2011/049249

申请日：2011-08-25

Applicant: PACIFIC BIOSCIENCES OF CALIFORNIA, INC. ,  SHEN, Gene ,  SEBO, Lubomir ,  YUE, Stephen ,  SUN, David ,  BROGLEY, Louis ,  FEDEROV, Andrei

Inventor： SHEN, Gene ,  SEBO, Lubomir ,  YUE, Stephen ,  SUN, David ,  BROGLEY, Louis ,  FEDEROV, Andrei

IPC: C12N11/00 ,  C07D403/04 ,  C07D251/12 ,  C12Q1/68 ,  C12Q1/25 ,  G01N33/52

Abstract: The invention provides a novel class of scaffold-based labeled polymerase enzyme substrates. The polymerase enzyme substrates have a multivalent core or scaffold to which is attached fluorescent dye moieties and nucleoside phosphate moities. The polymerase enzyme substrates have multiple fluorescent dye moities and/or multiple nucleoside phosphate moieties. Preferred multivalent cores comprise trifunctional six membered aromatic moities. The invention also provides for sequencing methods and kits with scaffold-based labeled polymerase enzyme substrates.

公开(公告)号：WO2010059880A2

公开(公告)日：2010-05-27

申请号：PCT/US2009065222

申请日：2009-11-19

Applicant: PACIFIC BIOSCIENCES CALIFORNIA ,  KONG XIANGXU ,  SHEN GENE ,  FEDEROV ANDREI ,  LYLE JOHN ,  LEE GRACE ,  SEBO LUBOMIR ,  DO DUC ,  WEBER ROBERT ,  DUDEK STEVE

Inventor： KONG XIANGXU ,  SHEN GENE ,  FEDEROV ANDREI ,  LYLE JOHN ,  LEE GRACE ,  SEBO LUBOMIR ,  DO DUC ,  WEBER ROBERT ,  DUDEK STEVE

IPC: G01N33/52 ,  C07C50/04 ,  C12Q1/48

CPC classification number: C07C49/255 ,  G01N21/6428 ,  G01N33/5306 ,  G01N2021/6432

Abstract: Compositions, devices, systems and methods for reducing and/or preventing photo-induced damage of one or more reactants in an illuminated analytical reaction by addition of one or more photo-induced damage mitigating agents to the reaction mixture and allowing the reaction to proceed for a period that is less than a photo-induced damage threshold period.

Abstract translation: 用于通过向反应混合物添加一种或多种光诱导损伤缓解剂并允许反应进行以减少和/或防止照射分析反应中一种或多种反应物的光诱导损伤的组合物，装置，系统和方法 小于光诱导损伤阈值时间的时间段。

公开(公告)号：WO2005024635A2

公开(公告)日：2005-03-17

申请号：PCT/US2004/018042

申请日：2004-06-04

Applicant: ADVANCED MICRO DEVICES, INC. ,  SHEN, Gene, W. ,  NELSON, S., Craig

Inventor： SHEN, Gene, W. ,  NELSON, S., Craig

IPC: G06F12/00

CPC classification number: G06F12/0864 ,  G06F9/3824 ,  G06F9/3832 ,  G06F12/1027 ,  G06F2212/6082 ,  G06F2212/652 ,  Y02D10/13

Abstract: A processor (10) comprises a cache (16), a first TLB (30), and a tag circuit (36). The cache (16) comprises a data memory (20) storing a plurality of cache lines and a tag memory (22) storing a plurality of tags. The first TLB (30) stores a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB (30). The tag circuit (36) is configured to identify one or more of the plurality of cache lines that are stored in the cache (16) and are within the plurality of virtual pages. In response to a hit by a first virtual address in the first TLB (30) and a hit by the first virtual address in the tag circuit (36), the tag circuit (36) is configured to prevent a read of the tag memory (22) in the cache (16).

Abstract translation: 处理器（10）包括高速缓存（16），第一TLB（30）和标签电路（36）。 高速缓存（16）包括存储多个高速缓存线的数据存储器（20）和存储多个标签的标签存储器（22）。 第一TLB（30）存储识别在第一TLB（30）中存储物理地址转换的多个虚拟页面的虚拟地址的多个页面部分。 标签电路（36）被配置为识别存储在高速缓存（16）中并且在多个虚拟页面内的多个高速缓存行中的一个或多个。 响应于第一TLB（30）中的第一虚拟地址的命中和标签电路（36）中的第一虚拟地址的命中，标签电路（36）被配置为防止标签存储器 22）在高速缓存（16）中。