公开(公告)号：US20250119056A1

公开(公告)日：2025-04-10

申请号：US18891647

申请日：2024-09-20

Applicant: STMicroelectronics International N.V.

Inventor： Fabio CACCIOTTO ,  Salvatore TORRISI

IPC: H02M1/42 ,  H02J7/02 ,  H02M1/00 ,  H02M3/335

Abstract: Provided is a power supply control circuit for a power supply, including a PFC converter configured to generate a bus voltage, an electronic converter and an auxiliary power supply configured to generate an auxiliary supply voltage. The PFC converter comprises a PFC control circuit configured to drive the PFC converter to regulate the bus voltage to a requested value. When the output power is greater than the threshold, the power supply control circuit supplies the PFC control circuit with the auxiliary supply voltage. When the output power is smaller than the threshold, the circuit compares the bus voltage to upper and lower thresholds. When the bus voltage is greater than the upper threshold, the circuit inhibits supply of the PFC control circuit with the auxiliary supply voltage. When the bus voltage is smaller than a lower threshold, the circuit supplies the PFC control circuit with the auxiliary supply voltage.

公开(公告)号：US20250118613A1

公开(公告)日：2025-04-10

申请号：US18892003

申请日：2024-09-20

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Paolo COLPANI ,  Luisito LIVELLARA

IPC: H01L23/31 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure generally provides for a high electron mobility transistor or HEMT. An example HEMT includes a first semiconductor layer; a gate arranged on a first surface of the first semiconductor layer; a first passivation layer comprising at least a sub-layer of a first dielectric material on the sides of the gate, the first passivation layer further extending over a first portion of the surface of the first semiconductor layer; and a second passivation layer, distinct from the first passivation layer, comprising at least a sub-layer of the same first dielectric material on a second portion of the surface of the first semiconductor layer next to the first passivation layer.

公开(公告)号：US20250117500A1

公开(公告)日：2025-04-10

申请号：US18896096

申请日：2024-09-25

Applicant: STMicroelectronics International N.V.

Inventor： Jean-Michel GRIL-MAFFRE ,  Christophe EVA

IPC: G06F21/60

Abstract: The present disclosure provides a system and method for reading an encryption/decryption key. An example includes at least one first word comprising a plurality of bits, with the system including: a first comparison means, a first delivery means, a second comparison means, and a second delivery means.

公开(公告)号：US12273089B2

公开(公告)日：2025-04-08

申请号：US17800277

申请日：2021-02-15

Applicant: STMicroelectronics International N.V.

Inventor： Guillaume Blamon ,  Emmanuel Picard ,  Christophe Boyavalle

IPC: H03H7/38 ,  H03F1/56 ,  H03F3/24 ,  H03H7/01 ,  H03H11/34 ,  H04B1/44

Abstract: The integrated circuit includes a power amplifier intended to provide a signal in a fundamental frequency band, an antenna, and a matching and filtering network having a first section, a second section, and a third section. The three sections include LC arrangements configured to have an impedance matched to the power amplifier's output in the fundamental frequency band. The LC arrangements of the first section and the second section are configured to have resonant frequencies adapted to attenuate the harmonic frequency bands of the fundamental frequency band.

公开(公告)号：US20250113511A1

公开(公告)日：2025-04-03

申请号：US18903368

申请日：2024-10-01

Applicant: STMicroelectronics International N.V.

Inventor： Edoardo BREZZA ,  Alexis GAUTHIER

IPC: H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737

Abstract: To manufacture a bipolar transistor, a first stack of layers including a first layer made of the material of the base of the bipolar transistor is formed between second and third insulating layers. A first cavity is then formed crossing the first stack in such a way as to reach the substrate. The forming of the first cavity includes an etching of no layer covering the first layer other than the third layer. A first portion of the collector of the bipolar transistor and a second portion of the base of the bipolar transistor are then formed in the first cavity.

公开(公告)号：US20250112596A1

公开(公告)日：2025-04-03

申请号：US18480322

申请日：2023-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Alessio Emanuele Vergani ,  Francesco Piscitelli ,  Michele Bartolini

IPC: H03F1/02 ,  H03K5/24 ,  H03K19/20

Abstract: According to an embodiment, an envelope detector circuit for detecting an envelope of a signal from a sensor in a pre-amplifier circuit of a hard disk drive is provided. The circuit includes a half-wave rectifier, a low-pass filter, and a differential full-wave rectifier. The half-wave rectifier receives a differential voltage from the sensor indicating a fly height of the hard disk drive and generates a pair of single-ended output waveforms based on the differential voltage. Each pair of single-ended output waveforms has a positive polarity for a half-cycle it passes through. The low-pass filter includes a first and a second low-pass filter. The low-pass filter allows low-frequency signals from the pair of single-ended output waveforms to pass through while attenuating or blocking higher-frequency signals. The differential full-wave rectifier reconstructs a differential signal from the low-pass filter while removing DC rectified components.

公开(公告)号：US20250112553A1

公开(公告)日：2025-04-03

申请号：US18480340

申请日：2023-10-03

Applicant: STMicroelectronics International N.V.

Inventor： Claudio Bona ,  Kien Beng Tan

IPC: H02M3/158 ,  H02J7/00 ,  H02M1/00

Abstract: According to an embodiment, a method of operating an M-level buck converter in a battery charging circuit is provided. The M-level buck converter includes 2×N×(M−1) number of transistors. M and N are greater than one. The method includes operating the M-level buck converter in a first mode of the battery charging circuit corresponding to a high-current charge mode. The method further includes operating the M-level buck converter in a second mode of the battery charging circuit corresponding to a low-current charge mode. In the first mode, 2×N×(M−1) number of transistors are switched ON and OFF. In the second mode, 2×(M−1) number of transistors are switched ON and OFF and 2×N×(M−1)−2×(M−1) number of transistors are fully deactivated.

公开(公告)号：US20250112492A1

公开(公告)日：2025-04-03

申请号：US18478553

申请日：2023-09-29

Applicant: STMicroelectronics International N.V.

Inventor： Roberto LA ROSA

IPC: H02J7/34 ,  H02J7/00

Abstract: Disclosed is an energy autonomous system including an energy transducer, a first capacitor, a second capacitor having greater capacitance than the first capacitor, and a microprocessor. The microprocessor includes a first terminal electrically coupled to the energy transducer and the first capacitor; a second terminal electrically coupled to the second capacitor; a switch that is in a conductive state in which the switch electrically couples the first terminal and second terminals together, or a nonconductive state in which the switch does not electrically couple first terminal and second terminals together; a voltage detector that detects a voltage at the first terminal; and a processor coupled to the voltage detector and the switch. The processor controls charging of the second capacitor by controlling the switch to be in the conductive state or the nonconductive state based on the voltage at the first terminal detected by the voltage detector.

公开(公告)号：US20250112350A1

公开(公告)日：2025-04-03

申请号：US18478758

申请日：2023-09-29

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  INSTITUT POLYTECHNIQUE DE GRENOBLE ,  UNIVERSITE GRENOBLE ALPES

Inventor： David OUATTARA ,  Cedric DURAND ,  Frederic PAILLARDET

IPC: H01P1/18 ,  H03H7/18 ,  H03H11/20

Abstract: Various embodiments of the present disclosure provide a phase shifter including a plurality of digital phase shifters, each digital phase shifter of the plurality of the digital phase shifters configured to vary a phase of a phase shifter input signal by a corresponding phase shift value, and a continuous phase shifter configured to vary the phase of the phase shifter input signal with a variable phase shift value. In various embodiments, the continuous phase shifter comprises a continuous phase shifter load configured to receive a control voltage and vary the variable phase shift value using the control voltage.

公开(公告)号：US20250111878A1

公开(公告)日：2025-04-03

申请号：US18883201

申请日：2024-09-12

Applicant: STMicroelectronics International N.V.

Inventor： Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfré ,  Massimo Caruso ,  Maurizio Francesco Perroni

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/28

Abstract: A row decoder circuit includes an input node receiving a row selection signal and an output node coupled to a memory device word line. A pull-down circuit couples the word line to ground in response to the row selection signal being asserted. A pull-up circuit couples the word line to a supply node in response to a deselection signal being de-asserted. An inverter circuit receives as input a control signal from a control node and produces the deselection signal. A current generator sources a biasing current to the control node. A further pull-down circuit couples the control node to ground in response to the row selection signal being asserted, and comprises a first cascode n-channel transistor, a cascode p-channel transistor, a second cascode n-channel transistor, and at least one selection transistor controlled by the row selection signal, all having their conductive channels arranged in series.