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    DISPOSITIF DE REGULATION A FAIBLE CHUTE DE TENSION, EN PARTICULIER CAPABLE DE SUPPORTER DES TENSIONS D'ALIMENTATION COMPATIBLES AVEC LA NORME USB TYPE C
    21.
    发明专利
    DISPOSITIF DE REGULATION A FAIBLE CHUTE DE TENSION, EN PARTICULIER CAPABLE DE SUPPORTER DES TENSIONS D'ALIMENTATION COMPATIBLES AVEC LA NORME USB TYPE C 未知

    公开(公告)号：FR3051570A1

    公开(公告)日：2017-11-24

    申请号：FR1654576

    申请日：2016-05-23

    Applicant: STMICROELECTRONICS (ALPS) SAS

    Inventor： PONS ALEXANDRE

    IPC: G05F1/10 ,  G06F13/38

    Abstract: Dispositif de régulation à faible chute de tension, comprenant un amplificateur d'erreur (AE) et un étage de puissance (ETP) ayant une borne de sortie (BS) rebouclée sur l'amplificateur d'erreur (AE) et apte à délivrer un courant de sortie dans une charge (RL, CL). Le dispositif comprend plusieurs entrées principales d'alimentation (EALPi) destinées à potentiellement recevoir respectivement plusieurs tensions d'alimentation différentes, en ce que l'étage de puissance (ETP) comprend plusieurs chemins de conduction (PTHi) respectivement connectés entre lesdites entrées principales d'alimentation et ladite borne de sortie, individuellement sélectionnables et comportant chacun un transistor de sortie (MPgi), en ce qu'il comprend en outre un circuit de sélection (CSL) connecté auxdites entrées principales d'alimentation et configuré pour sélectionner l'un des chemins de conduction (PTHi) en fonction d'un critère de sélection, et en ce que l'amplificateur d'erreur (AE) comporte un étage de sortie (ETS) configuré pour piloter sélectivement le transistor de sortie (MPgi) du chemin de conduction sélectionné.

    Spannungsquelle
    22.
    发明专利
    Spannungsquelle 未知

    公开(公告)号：DE102016102976A1

    公开(公告)日：2017-02-09

    申请号：DE102016102976

    申请日：2016-02-19

    Applicant: STMICROELECTRONICS (ALPS) SAS

    Inventor： LENZ KUNO

    IPC: H02M1/08 ,  H02P7/285

    Abstract: Die Erfindung betrifft eine Spannungsquelle, wobei mindestens ein erster Schalter (NM1) einen ersten Knoten (9) der Spannungsquelle mit einem Knoten (15) zum Anlegen mindestens eines Potenzials einer Versorgungsspannung koppelt, und mindestens ein erstes kapazitives Element (C1) den ersten Knoten oder einen zweiten Knoten (11) der Spannungsquelle mit einem Steuerknoten (G1) des ersten Schalters koppelt.

    Devices and methods to secure a system on a chip
    24.
    发明授权
    Devices and methods to secure a system on a chip 有权

    公开(公告)号：US12229253B2

    公开(公告)日：2025-02-18

    申请号：US17340164

    申请日：2021-06-07

    Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics International N.V.

    Inventor： Asif Rashid Zargar ,  Gilles Eyzat ,  Charul Jain

    IPC: G06F21/55

    Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

    ENVELOPE DETECTION
    25.
    发明申请
    ENVELOPE DETECTION 有权

    公开(公告)号：US20250055492A1

    公开(公告)日：2025-02-13

    申请号：US18929262

    申请日：2024-10-28

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

    Inventor： Danika Perrin ,  Sandrine Nicolas

    IPC: H04B1/16

    Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

    ANTENNA PACKAGE
    29.
    发明公开
    ANTENNA PACKAGE 审中-公开

    公开(公告)号：US20240120638A1

    公开(公告)日：2024-04-11

    申请号：US18545106

    申请日：2023-12-19

    Applicant: STMicroelectronics (Alps) SAS

    Inventor： Deborah COGONI

    IPC: H01Q1/12 ,  H01Q1/38

    CPC classification number: H01Q1/12 ,  H01Q1/38

    Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.

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