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公开(公告)号：US20200287507A1
公开(公告)日：2020-09-10
申请号：US16291971
申请日：2019-03-04
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： Ru Feng Du , XiangSheng Li
Abstract: In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.
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公开(公告)号：US10749515B1
公开(公告)日：2020-08-18
申请号：US16669154
申请日：2019-10-30
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Hong Wu Lin
Abstract: A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.
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23.发明授权公开(公告)号：US10719114B2
公开(公告)日：2020-07-21
申请号：US15966808
申请日：2018-04-30
Inventor： Andy Lin , Johnny Yoon , Danny Sheng
Abstract: An embodiment is a circuit for use with a display device, the circuit including: a first input node configured to be operatively coupled to a first port of a data source device that provides the display device with data, to receive a first direct voltage used for a real-time display of the data on the display device; and at least one output node, configured to operatively provide the display device with at least one output voltage generated based on the first direct voltage, wherein the first port is isolated from a data port used to transmit the data.
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公开(公告)号：US10122279B2
公开(公告)日：2018-11-06
申请号：US15592757
申请日：2017-05-11
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Hai Bo Zhang , Jerry Huang
Abstract: A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver.
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公开(公告)号：US10073484B2
公开(公告)日：2018-09-11
申请号：US15671657
申请日：2017-08-08
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Yong Feng Liu
IPC: G05F3/26
CPC classification number: G05F3/267
Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.
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Patent Agency Ranking
公开(公告)号：US20180026598A1
公开(公告)日：2018-01-25
申请号：US15723622
申请日：2017-10-03
Inventor： XiangSheng Li , Cristiano Meroni , Mei Yang , Xian Feng Xiong
CPC classification number: H03G3/348 , H03F1/52 , H03F3/183 , H03F3/21 , H03F2200/321 , H03F2200/375 , H03F2200/471 , H03F2200/78 , H03G11/00 , H04R1/00 , H04R3/007 , H04R2201/028 , H04R2499/13
Abstract: A circuit can be used in a speaker system. The circuit includes an amplifier with an output configured to be coupled to a speaker. An offset comparator has an input coupled the output of the amplifier and is configured to provide an offset control signal. A digital circuit has a first input coupled to an output of the offset comparator, a second input configured to receive an amplifier control signal, a third input configured to receive a play control signal, and an output configured to provide a forced mute signal that can be used to control the amplifier.
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公开(公告)号：US09866187B2
公开(公告)日：2018-01-09
申请号：US14715879
申请日：2015-05-19
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Qi Yu Liu , Hong Wu Lin
CPC classification number: H03F3/183 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/03 , H03F2203/45138
Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.
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公开(公告)号：US20170330989A1
公开(公告)日：2017-11-16
申请号：US15668138
申请日：2017-08-03
Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO., LTD.
Inventor： Jing-En Luan
IPC: H01L31/173 , G01S17/02 , G01S7/481 , H01L23/00 , H01L31/0203 , H01L31/0232 , G01S17/08
CPC classification number: H01L31/173 , G01S7/4813 , G01S17/026 , G01S17/08 , H01L24/19 , H01L31/0203 , H01L31/02327 , H01L2224/48091 , H01L2224/73265 , H01L2224/8592 , H01L2924/12041 , H01L2924/181 , H01L2924/00014 , H01L2924/00
Abstract: A proximity detector device may include a first interconnect layer including a first dielectric layer, and first electrically conductive traces carried thereby, an IC layer above the first interconnect layer and having an image sensor IC, and a light source IC laterally spaced from the image sensor IC. The proximity detector device may include a second interconnect layer above the IC layer and having a second dielectric layer, and second electrically conductive traces carried thereby. The second interconnect layer may have first and second openings therein respectively aligned with the image sensor IC and the light source IC. Each of the image sensor IC and the light source IC may be coupled to the first and second electrically conductive traces. The proximity detector device may include a lens assembly above the second interconnect layer and having first and second lenses respectively aligned with the first and second openings.
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公开(公告)号：US09791883B2
公开(公告)日：2017-10-17
申请号：US15218605
申请日：2016-07-25
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Meng Wang , Xue Lian Zhou
CPC classification number: G05F3/262 , H02M1/08 , H02M3/158 , H02M2001/0032 , Y02B70/16
Abstract: An electronic device disclosed herein includes a current comparator to generate an output current based upon a difference between a current flowing in an output branch and a current flowing in an input branch. A pair of transistors is coupled to an output of the current comparator. A first amplifier has inputs coupled to the pair of transistors and to a reference voltage, the first amplifier being configured to subtract the reference voltage from a voltage across the pair of transistors and output a difference voltage. A second amplifier has inputs coupled to the difference voltage and to the reference voltage, the second amplifier being configured to subtract the difference voltage from the reference voltage and output a pulse skipping mode reference signal.
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公开(公告)号：US20170146571A1
公开(公告)日：2017-05-25
申请号：US14955207
申请日：2015-12-01
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Meng Wang , Xue Lian Zhou
IPC: G01R15/18
CPC classification number: G01R15/18 , G01R15/16 , G01R19/16538
Abstract: Current flowing through an inductor in response to a pulse width modulation (PWM) control signal is sensed to generate a sensed current. The sensed current is processed over one or more PWM cycles of the PWM control signal to generate an output signal indicative of average inductor current. This processing may include charging and discharging a capacitor at different rates dependent on the sense current, with the detection of capacitor discharge triggering a sampling of a voltage dependent on the sensed current that is indicative of average inductor current. The processing may include using the sensed to current to generate a first charge voltage associated with minimum inductor current and a second charge voltage associated with maximum inductor current, and then averaging the first and second charge voltages to generate an output signal indicative of average inductor current.
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