公开(公告)号：US20040205096A1

公开(公告)日：2004-10-14

申请号：US10757836

申请日：2004-01-16

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F007/38

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and system for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.

Abstract translation: 一种可编程处理器和系统，用于通过结合执行单元来操作以解码和执行指定包含多个数据元素的三个寄存器的单个指令来提高处理器的性能，所述执行单元可操作以将第一和第二寄存器相乘并将第三寄存器 以产生包含多个数据元素的连接结果。 附加指令提供组浮点减法，加，乘，少设置和设置更大的相等操作。 集合较少和设置较大相等的操作为连接结果的每个元素产生替代零或身份元素，结果便于使用逐位布尔运算而不需要条件分支操作来替代选择各个数据元素。

公开(公告)号：US20040199750A1

公开(公告)日：2004-10-07

申请号：US10646787

申请日：2003-08-25

Applicant: MICRO UNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/00

CPC classification number: G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3834 ,  G06F12/0875

Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.

Abstract translation: 一种可编程处理器，其包括能够独立于另一主机处理器的操作的通用处理器架构，具有虚拟存储器寻址单元，指令路径和数据路径; 外部接口; 缓存，用于保持在所述外部接口和所述数据路径之间传送的数据; 至少一个寄存器文件，其被配置为从所述数据路径接收和存储数据并将所存储的数据传送到所述数据路径; 以及耦合到数据路径的多精度执行单元。 多精度执行单元可配置为动态分割从数据路径接收到的数据，以考虑数据的基本宽度，并且能够对操作数寄存器的分区字段中的多个操作数执行组浮点运算，并返回联结结果。 在其他实施例中，多精度执行单元另外可配置为执行组整数和/或组数据处理操作。

公开(公告)号：US20040158689A1

公开(公告)日：2004-08-12

申请号：US10716568

申请日：2003-11-20

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F012/00

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.

Abstract translation: 一种用于通过并入执行单元的系统和软件，所述执行单元可操作以对指令集中的单个指令进行解码和执行，所述指令集包括：（a）在寄存器的分割字段中对多个数据元素进行操作的组指令， 结果，（b）对齐的存储器操作，在存储器和寄存器之间移动数据，存储器操作数对齐，以及（c）存储器操作数未对齐的未对齐的存储器操作。

公开(公告)号：US20040098567A1

公开(公告)日：2004-05-20

申请号：US10712430

申请日：2003-11-14

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F009/44

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the execution unit is operable to shift a subfield of each of the plurality of data elements by the shift amount to produce a second plurality of data elements; and provide the second plurality of data elements as a catenated result.

Abstract translation: 一种可编程处理器和方法，用于通过结合执行单元来提高处理器的性能，所述执行单元可操作以解码和执行指定移位量的单个指令和包含多个数据元素的寄存器，其中所述执行单元可操作以移位每个 多个数据元素的移位量产生第二多个数据元素; 并且提供第二多个数据元素作为连接结果。

公开(公告)号：WO2013142579A1

公开(公告)日：2013-09-26

申请号：PCT/US2013/033108

申请日：2013-03-20

Applicant: AERO SYSTEMS ENGINEERING, INC. ,  CHENG, Chunyuen, R. ,  NATHAN, Thomas, H.

Inventor： CHENG, Chunyuen, R. ,  NATHAN, Thomas, H.

IPC: G10K11/00

CPC classification number: F01N1/084 ,  G10K11/161

Abstract: A matrix or array of elongated tubular members, each member being formed by spirally winding a piece or pieces of material into a generally cylindrical shape, wherein the matrix or array is mounted in an airflow to reduce the noise associated with and/or produced by the airflow.

Abstract translation: 每个构件通过将一片或多片材料螺旋地卷绕成大致圆柱形的形状而形成的矩形或阵列的细长管状构件，其中矩阵或阵列安装在气流中以减少与由...组成的和/或由 气流。

公开(公告)号：WO2012048429A1

公开(公告)日：2012-04-19

申请号：PCT/CA2011/050646

申请日：2011-10-13

Applicant: ADAMSON SYSTEMS ENGINEERING INC. ,  ADAMSON, Alan Brock ,  CABOT, Ben ,  MCDONALD, Ewan James

Inventor： ADAMSON, Alan Brock ,  CABOT, Ben ,  MCDONALD, Ewan James

IPC: H04R1/02 ,  A47B81/00 ,  A47B96/06 ,  B66C1/00 ,  F16B1/00

CPC classification number: H04R1/026 ,  H04R1/403 ,  H04R27/00

Abstract: Disclosed herein is a rigging component for connecting a loudspeaker array element in an array. The rigging component is configured for releasably attaching one array element to another array element via a connection link that is slidably extendable from a housing. The housing includes a conduit for receiving a connection link of an adjacent rigging component. A latching device is provided for retaining the connection link of the adjacent rigging component within the conduit. An additional latching device may be included for releasably locking the connection link of the rigging component at one or more positions for controlling a relative separation of adjacent array elements.

Abstract translation: 这里公开了用于连接阵列中的扬声器阵列元件的索具部件。 索具部件构造成通过可从壳体可滑动地延伸的连接连杆将一个阵列元件可释放地附接到另一个阵列元件。 壳体包括用于接收相邻索具部件的连接连杆的导管。 提供了一种闭锁装置，用于将相邻的索具部件的连接连杆保持在导管内。 可以包括另外的闩锁装置，用于可释放地将索具部件的连接链节锁定在一个或多个位置，以控制相邻阵列元件的相对间隔。

公开(公告)号：WO2012048428A1

公开(公告)日：2012-04-19

申请号：PCT/CA2011/050645

申请日：2011-10-13

Applicant: ADAMSON SYSTEMS ENGINEERING INC. ,  ADAMSON, Alan Brock

Inventor： ADAMSON, Alan Brock

IPC: H04R1/02

CPC classification number: H04R5/02 ,  H04R1/025 ,  H04R1/026 ,  H04R1/403 ,  H04R27/00

Abstract: A loudspeaker array element with an internal rigid structural frame and at least one interface for attaching one or more of enclosures, rigging components, waveguides, sound chambers, transducers and electronics to the frame is provided. Further configurations are provided for heat sinking of electrically powered devices such as loudspeakers, as well as power amplifiers, digital signal processing and networking hardware.

Abstract translation: 提供具有内部刚性结构框架的扬声器阵列元件和用于将一个或多个外壳，索具部件，波导，声室，换能器和电子器件连接到框架的至少一个接口。 还提供了用于诸如扬声器的电力设备的散热以及功率放大器，数字信号处理和网络硬件的其它配置。

公开(公告)号：WO2003021423A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027970

申请日：2002-09-04

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  BATEMAN, Bruce ,  MOUSSOURIS, John

IPC: G06F7/00

CPC classification number: G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

Abstract: The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multipliers regardsless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

Abstract translation: 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 随着操作数大小减小，矩阵和向量操作数的元素数量增加，功能单元完全利用128b乘128b乘法器的全部资源，而不考虑操作数大小。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

公开(公告)号：WO1997014094A1

公开(公告)日：1997-04-17

申请号：PCT/US1996016320

申请日：1996-10-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F09/302

CPC classification number: G06F9/30189 ,  G06F9/30014 ,  G06F9/3865

Abstract: A floating-point instruction having incorporated floating point information and a method and system for implementing the floating-point instruction in a computer system is described. The floating point information indicates whether an exception trap should occur and the type of rounding to be performed upon "inexact" arithmetic results. The floating point information further indicates whether other floating-point exception traps should occur. This information allows dynamic (e.g. instruction-by-instruction) modification of various operating parameters of the CPU without modifying information in status registers using special instructions or modes, thereby increasing overall CPU performance. The technique is also supported by several mechanisms for providing precise floating-point exceptions.

Abstract translation: 描述了包含浮点信息的浮点指令以及用于在计算机系统中实现浮点指令的方法和系统。 浮点信息指示是否发生异常陷阱，并在“不精确”运算结果时执行舍入的类型。 浮点信息还指示是否应发生其他浮点异常捕获。 该信息允许在不使用特殊指令或模式修改状态寄存器中的信息的情况下对CPU的各种操作参数进行动态（例如逐个指令）修改，从而提高整体CPU性能。 该技术还通过几种提供精确浮点异常的机制来支持。

公开(公告)号：WO1997007451A2

公开(公告)日：1997-02-27

申请号：PCT/US1996013195

申请日：1996-08-14

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  KARZES, Thomas, J. ,  HANSEN, Craig, C. ,  MASSALIN, Henry

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F07/00

CPC classification number: G06F7/762 ,  G06F7/76 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032

Abstract: A method and system for performing arbitrary permutations of sequences of elements. In the general case, the method of the present invention processes the elements to be permuted as a multi-dimensional array, where each element in the array corresponds to one of the elments to be permuted. The permutation is achieved by performing a sequence of sets of permutations, where each set of permutations in the sequence independently permutes the elements within each one-dimensional slice through the array, along some particular dimension of the array. The total number of sets of permutations, or stages, is one less than twice the number of dimensions in the array. An extension to the general method allows some extensions of permutations which involve the copying of individual elements. A system based on the extended general method implements a large class of operations which involve copying and/or permuting elements, where the sequence of elements is a word of data and the elements are bits of data. An efficient control structure for the system permits control signals to be shared across slices of the array. A version of the system based on a two-dimensional array includes three multiplex stages, where the first stage multiplexes along the rows, the second stage multiplexes along the columns, and the third stage multiplexes across the rows once again. Several classes of computer instructions which generally involve the copying and/or permuting of data are also described.

Abstract translation: 一种用于执行元素序列的任意排列的方法和系统。 在一般情况下，本发明的方法将要置换的元素处理为多维阵列，其中阵列中的每个元素对应于待置换的元素中的一个。 通过执行一组排列来实现置换，其中序列中的每组置换通过阵列沿着阵列的某个特定维度独立地排列每个一维切片内的元素。 排列的集合或阶段的总数量是数组中维度数量的两倍。 一般方法的扩展允许一些涉及复制单个元素的排列扩展。 基于扩展通用方法的系统实现涉及复制和/或置换元素的大类操作，其中元素序列是数据字，元素是数据位。 该系统的有效的控制结构允许控制信号在阵列的切片之间共享。 基于二维阵列的系统的版本包括三个复用级，其中第一级沿着行多路复用，第二级沿着列多路复用，并且第三级再次跨越行多路复用。 还描述了通常涉及数据的复制和/或置换的几类计算机指令。