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    Multi-port memory device providing protection signal
    21.
    发明申请
    Multi-port memory device providing protection signal 失效

    公开(公告)号：US20060161338A1

    公开(公告)日：2006-07-20

    申请号：US11345054

    申请日：2006-02-01

    Applicant: Han-Gu Sohn ,  Woon-Sik Suh ,  Yun-Tae Lee ,  Sei-Jin Kim

    Inventor： Han-Gu Sohn ,  Woon-Sik Suh ,  Yun-Tae Lee ,  Sei-Jin Kim

    IPC: G01C21/34

    CPC classification number: G11C7/1075 ,  G06F13/1647 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096

    Abstract: A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.

    Microcomputer systems having compressed instruction processing capability and methods of operating same
    23.
    发明授权
    Microcomputer systems having compressed instruction processing capability and methods of operating same 有权
    具有压缩指令处理能力的微机系统及其操作方法

    公开(公告)号：US06654874B1

    公开(公告)日：2003-11-25

    申请号：US09536435

    申请日：2000-03-27

    Applicant: Yun-Tae Lee

    Inventor： Yun-Tae Lee

    IPC: G06F930

    CPC classification number: G06F9/30178 ,  G06F9/30189

    Abstract: Microcomputer systems include an instruction processor therein that can process both normal length instructions and compressed instructions. The normal length instructions and the compressed instructions are provided from memory to an instruction register and then passed through decoding circuitry to a processor core. The decoding circuitry preferably comprises a demultiplexer having a data input that receives a first multi-bit instruction from the instruction register and a select input that receives a first select signal (SEL1). A compressed instruction decoder is also provided. The compressed instruction decoder has a data input electrically coupled to a first data output of the demultiplexer and a select input that receives a second select signal (SEL2). A multiplexer is also provided. The multiplexer has a first data input electrically coupled to an output of the compressed instruction decoder, a second data input electrically coupled to a second data output of the demultiplexer and a select input that receives the first select signal (SEL1). The output of the demultiplexer is electrically coupled to the processor core.

    Abstract translation: 微计算机系统包括其中可以处理正常长度指令和压缩指令的指令处理器。 正常长度指令和压缩指令从存储器提供给指令寄存器，然后通过解码电路传递到处理器核心。 解码电路优选地包括具有从指令寄存器接收第一多位指令的数据输入和接收第一选择信号（SEL1）的选择输入的解复用器。 还提供了压缩指令解码器。 压缩指令解码器具有电耦合到解复用器的第一数据输出的数据输入和接收第二选择信号（SEL2）的选择输入。 还提供多路复用器。 多路复用器具有电耦合到压缩指令解码器的输出端的第一数据输入端，电耦合到解复用器的第二数据输出端的第二数据输入端和接收第一选择信号（SEL1）的选择输入端。 多路分解器的输出电耦合到处理器核心。

    Methods of booting application processors from external devices
    27.
    发明授权
    Methods of booting application processors from external devices 有权
    从外部设备引导应用处理器的方法

    公开(公告)号：US08291210B2

    公开(公告)日：2012-10-16

    申请号：US12986264

    申请日：2011-01-07

    Applicant: Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

    Inventor： Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

    IPC: G06F9/24

    CPC classification number: G06F9/4401

    Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

    Abstract translation: 电子信息系统包括外部存储装置和应用处理器。 外部存储装置存储引导代码，并且应用处理器适于从外部存储设备接收引导代码，并且在上电操作期间通过执行引导代码执行系统引导操作。

    ECC controller for use in flash memory device and memory system including the same
    28.
    发明授权
    ECC controller for use in flash memory device and memory system including the same 有权
    用于闪存器件的ECC控制器和包括其的存储器系统

    公开(公告)号：US08112689B2

    公开(公告)日：2012-02-07

    申请号：US11785719

    申请日：2007-04-19

    Applicant: Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

    Inventor： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

    IPC: H03M13/00

    CPC classification number: H03M13/2945 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/29 ,  H03M13/2906

    Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

    Abstract translation: 存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块， 根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块， ，第一ECC数据和第二ECC数据被存储在闪存设备中。

    MEMORY SYSTEM AND MEMORY MANAGEMENT METHOD INCLUDING THE SAME
    29.
    发明申请
    MEMORY SYSTEM AND MEMORY MANAGEMENT METHOD INCLUDING THE SAME 有权
    包括其内存系统和内存管理方法

    公开(公告)号：US20110119477A1

    公开(公告)日：2011-05-19

    申请号：US13014328

    申请日：2011-01-26

    Applicant: Sung-Jae Byun ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

    Inventor： Sung-Jae Byun ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

    IPC: G06F15/177

    CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F15/177 ,  G11C8/16 ,  Y02D10/13

    Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

    Abstract translation: 多处理器系统包括第一处理器，与第一处理器通信的第二处理器，用于存储第一代码和第二代码以分别引导第一和第二处理器的第一非易失性存储器，可与第一处理器通信的第一存储器， 为第一处理器指定的第二易失性存储器，为第二处理器指定的第三易失性存储器，以及由第一和第二处理器共享的第四易失性存储器。

    System comprising electronic device and external device storing boot code for booting system
    30.
    发明申请
    System comprising electronic device and external device storing boot code for booting system 有权
    包括电子设备和外部设备的系统存储引导系统的引导代码

    公开(公告)号：US20070277027A1

    公开(公告)日：2007-11-29

    申请号：US11797985

    申请日：2007-05-09

    Applicant: Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

    Inventor： Yong-Hoon Kim ,  Yun-Tae Lee ,  Sung-Up Choi

    IPC: G06F15/177

    CPC classification number: G06F9/4401

    Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

    Abstract translation: 电子信息系统包括外部存储装置和应用处理器。 外部存储装置存储引导代码，并且应用处理器适于从外部存储设备接收引导代码，并且在上电操作期间通过执行引导代码执行系统引导操作。

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