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    METHOD OF ROOM TEMPERATURE COVALENT BONDING
    21.
    发明专利
    METHOD OF ROOM TEMPERATURE COVALENT BONDING 未知

    公开(公告)号：CA2526481A1

    公开(公告)日：2004-12-02

    申请号：CA2526481

    申请日：2004-05-19

    Applicant: ZIPTRONIX INC

    Inventor： TONG QIN-YI

    IPC: H01L21/02 ,  B81C1/00 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/58 ,  H01L21/762 ,  H01L23/535 ,  H01L27/00 ,  H01L29/12

    Abstract: A method of bonding includes using a bonding layer having a fluorinated oxid e. Fluorine may be introduced into the bonding layer by exposure to a fluorine- containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bondin g layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

    SYSTEMS AND METHODS FOR EFFICIENT TRANSFER OF SEMICONDUCTOR ELEMENTS
    22.
    发明申请
    SYSTEMS AND METHODS FOR EFFICIENT TRANSFER OF SEMICONDUCTOR ELEMENTS 审中-公开
    用于半导体元件有效转移的系统和方法

    公开(公告)号：WO2017123407A1

    公开(公告)日：2017-07-20

    申请号：PCT/US2016/068577

    申请日：2016-12-23

    Applicant: ZIPTRONIX, INC.

    Inventor： UZOH, Cyprian Emeka ,  ENQUIST, Paul M. ,  FOUNTAIN, Jr., Gaius Gillman

    IPC: H01L21/683 ,  H01L21/687

    CPC classification number: H01L25/50 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L25/105 ,  H01L2221/68327

    Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.

    Abstract translation: 公开了用于有效传递元素的系统和方法。 可以提供支撑多个切块集成装置模具的膜。 多个切割后的集成器件管芯可以沿着膜的表面彼此相邻布置。 可以将膜定位在支撑结构附近，使得膜的表面面对支撑结构的支撑表面。 该膜可以选择性地相对于支撑结构横向定位，使得选定的第一模具与支撑结构的第一位置对齐。 可以在不平行于膜表面的方向上施加力，以使所选择的第一模具直接从膜转移到支撑结构。

    WAFER SCALE DIE HANDLING
    23.
    发明申请
    WAFER SCALE DIE HANDLING 审中-公开

    公开(公告)号：WO2005091868A2

    公开(公告)日：2005-10-06

    申请号：PCT/US2005/005641

    申请日：2005-02-23

    Applicant: ZIPTRONIX, INC. ,  ENQUIST, Paul, M. ,  FOUNTAIN, Gaius, G., Jr. ,  PETTEWAY, Carl, T.

    Inventor： ENQUIST, Paul, M. ,  FOUNTAIN, Gaius, G., Jr. ,  PETTEWAY, Carl, T.

    IPC: H01L23/495

    CPC classification number: H01L21/67333 ,  H01L2924/0002 ,  Y10S414/135 ,  Y10S414/14 ,  Y10S414/141 ,  H01L2924/00

    Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

    Abstract translation: 一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。 该元件与半导体晶片处理设备和/或半导体晶片处理兼容。 优选地，构件容纳来自半导体晶片的至少大部分管芯。 此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置去除管芯，将来自单个瓦楞纸包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将 放置在半导体封装中以形成集成电路。 提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将 放置在半导体封装中以形成集成电路。

    CONDUCTIVE BARRIER DIRECT HYBRID BONDING
    25.
    发明申请
    CONDUCTIVE BARRIER DIRECT HYBRID BONDING 审中-公开
    导电障碍物直接混合结合

    公开(公告)号：WO2017035321A1

    公开(公告)日：2017-03-02

    申请号：PCT/US2016/048609

    申请日：2016-08-25

    Applicant: ZIPTRONIX, INC.

    Inventor： ENQUIST, Paul, M.

    IPC: H01L21/18 ,  H01L21/52 ,  H01L23/00

    CPC classification number: H01L24/09 ,  H01L21/50 ,  H01L24/03 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/036 ,  H01L2224/05005 ,  H01L2224/05078 ,  H01L2224/05082 ,  H01L2224/08145 ,  H01L2224/8019 ,  H01L2224/80895 ,  H01L2225/06513

    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non- metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

    Abstract translation: 一种用于形成直接杂化键的方法和由直接杂化键形成的器件，其包括具有第一组金属接合焊盘的第一衬底，该第一衬底优选地连接到被导电屏障封盖的器件或电路上， 金属区域，与第一基板上的金属接合焊盘相邻，第二基板具有由第二导电屏障覆盖的第二组金属接合焊盘，第二组导电屏障与第一组金属焊盘对准，优选地连接到器件或电路，以及 具有与第二基板上的金属接合焊盘相邻的第二非金属区域，以及由第一非金属区域与第一非金属区域接触形成的导电屏障封住的第一和第二组金属接合焊盘之间的接触接合界面 第二个非金属区域。

    INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING
    28.
    发明申请
    INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING 审中-公开
    增加接触对齐公差以直接结合

    公开(公告)号：WO2017106650A1

    公开(公告)日：2017-06-22

    申请号：PCT/US2016/067182

    申请日：2016-12-16

    Applicant: ZIPTRONIX, INC.

    Inventor： ENQUIST, Paul, M. ,  FOUNTAIN, Gaius, Gillman ,  DELACRUZ, Javier, A.

    IPC: H01L21/52 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00

    CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L23/5226 ,  H01L24/02 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/80 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593

    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non- metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

    Abstract translation: 包括具有第一组导电触点结构的第一衬底，所述第一组导电触点结构优选连接到器件或电路，并且具有与第一衬底上的触点结构相邻的第一非金属区域 具有第二组导电触点结构的第二衬底，所述第二组导电触点结构优选连接到器件或电路，并具有与所述第二衬底上的所述触点结构相邻的第二非金属区域，以及所述第一和第二触点之间的接触键合界面 通过第一非金属区与第二非金属区的接触结合形成的一组接触结构。 接触结构包括细长的接触特征，诸如在网格中连接的单独的线或线，其在两个基板上不平行，在交叉点处进行接触。 因此，对齐公差得到了改善，同时最大限度地减小了凹陷和寄生电容。

    WAFER SCALE DIE HANDLING
    30.
    发明申请
    WAFER SCALE DIE HANDLING 审中-公开

    公开(公告)号：WO2005091868A3

    公开(公告)日：2009-03-26

    申请号：PCT/US2005005641

    申请日：2005-02-23

    Applicant: ZIPTRONIX INC ,  ENQUIST PAUL M ,  FOUNTAIN GAIUS G JR ,  PETTEWAY CARL T

    Inventor： ENQUIST PAUL M ,  FOUNTAIN GAIUS G JR ,  PETTEWAY CARL T

    IPC: H01L23/495

    CPC classification number: H01L21/67333 ,  H01L2924/0002 ,  Y10S414/135 ,  Y10S414/14 ,  Y10S414/141 ,  H01L2924/00

    Abstract: A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

    Abstract translation: 一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。 该元件与半导体晶片处理设备和/或半导体晶片处理兼容。 优选地，构件容纳来自半导体晶片的至少大部分管芯。 此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置中去除裸片，将来自单个华夫饼包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将 放置在半导体封装中以形成集成电路。 提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将 放置在半导体封装中以形成集成电路。

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