公开(公告)号：KR100493884B1

公开(公告)日：2005-06-10

申请号：KR1020030001449

申请日：2003-01-09

Applicant: 삼성전자주식회사

Inventor： 서재유 ,  박찬익 ,  임재민

IPC: G06F12/00

CPC classification number: G06F12/0875 ,  G06F9/4403 ,  G06F9/44573 ,  G06F2212/2022

Abstract: 본 발명은 낸드형 플래시 메모리에서의 현지 실행을 위한 제어 장치 및 그 방법, 이를 이용한 플래시 메모리 칩에 관한 것이며, 소정의 저장 용량을 갖는 Serial FLASH 컨트롤러 장치에서 Serial FLASH에 접근하여 필요한 데이터가 속한 페이지 전체를 읽어들여 주 제어부로 요구된 데이터를 전송하거나 실행시켜 Serial FLASH에서의 XIP 기능 지원이 가능하도록 하는 것을 목적으로 한다.
이를 위해 Serial 플래시에서의 현지 실행을 위한 제어 장치는 시스템 인터페이스부를 통해 수신되는 주 제어부의 명령어에 따라 Serial FLASH의 지정된 메모리 주소를 액세스하여 상기 주 제어부로부터 요구된 데이터를 판독하거나 기록하는 캐시 모듈, Serial FLASH에 기록된 부트 코드를 독출하여 버퍼에 저장하고 상기 주 제어부로부터 부트 코드가 요구되면 바로 전송하여 시스템 부팅이 실행되도록 하는 부팅 로더가 구비되는 시리얼 플래시 컨트롤러, 캐시 모듈 및 시리얼 플래시 컨트롤러와 Serial FLASH간의 데이터 송/수신을 처리하는 플래시 인터페이스부를 포함하는 것을 특징으로 한다.

公开(公告)号：KR1020040064149A

公开(公告)日：2004-07-16

申请号：KR1020030001449

申请日：2003-01-09

Applicant: 삼성전자주식회사

Inventor： 서재유 ,  박찬익 ,  임재민

IPC: G06F12/00

CPC classification number: G06F12/0875 ,  G06F9/4403 ,  G06F9/44573 ,  G06F2212/2022

Abstract: PURPOSE: A device and a method for controlling the XIP(eXecute-In-Place) of a serial flash memory, and a flash memory chip using the same are provided to support an XIP function on the serial flash memory by transmitting/executing the needed data to a main controller after reading entire page including the needed data by accessing the serial flash memory to a serial flash memory controller. CONSTITUTION: A cache module reads/writes the data needed from the main controller(300) by accessing a set memory address of the serial flash memory(100) depending on an instruction of the main controller received through a system interface. A serial flash memory controller(500) is equipped with a boot loader executing system booting by reading a boot code recorded in the serial flash memory, storing the boot code in a buffer, and directly transmitting the boot code if the boot code is requested from the main controller. A flash memory interface transmits/receives the data between the cache module/boot loader and the serial flash memory.

Abstract translation: 目的：提供一种用于控制串行闪存的XIP（即时存储）的设备和方法以及使用该闪存的闪存芯片，以通过发送/执行所需的方式来支持串行闪存上的XIP功能 通过将串行闪存存入串行闪存控制器，读取包含所需数据的整个页面后的数据到主控制器。 构成：缓存模块根据通过系统接口接收的主控制器的指令，访问串行闪存（100）的设定存储器地址，读/写主控制器（300）所需的数据。 串行闪存控制器（500）配备有通过读取记录在串行闪存中的引导代码来执行系统引导的引导加载程序，将引导代码存储在缓冲器中，并且如果请求引导代码则直接传输引导代码 主控制器。 闪存接口在缓存模块/引导加载程序和串行闪存之间传输/接收数据。

公开(公告)号：KR1020010046715A

公开(公告)日：2001-06-15

申请号：KR1019990050595

申请日：1999-11-15

Applicant: 삼성전자주식회사

Inventor： 임재민

IPC: G06F15/16

CPC classification number: H04B10/801

Abstract: PURPOSE: A bus interface device for an optical module matching and a method thereof are provided to overcome a delay time which may be generated caused by a conversion between a digital signal and an optical signal of an optical module interface by delaying a driving of a signal permitting a use of data in the case that data are written for an optical module interface through the optical module interface on a bus. CONSTITUTION: A graphic data transmitting/receiving card(200) being connected to a peripheral component interconnect(PCI) is mounted on a PCI slot of a PC. The graphic data transmitting/receiving card(200) has a function for exchanging data between a CPU of the PC and a monitor unit(250) transmitting/receiving graphic data through an optical cable(240). The elements of the card(200) are described as follows. A bridge unit(210) processes an interface for connecting a PCI bus which is a system bus of the PC to the monitor unit(250). A card control unit(220) controls a data transmission between the bridge unit(210) and an optical signal conversion card module(230). The optical signal conversion card module(230) converts a digital signal transmitted from the card control unit(220) into an optical signal and outputs the optical signal to the monitor unit(250). Also, the optical signal conversion card module(230) converts the optical signal transmitted from the monitor unit(250) into a digital signal and outputs the digital signal to the card control unit(220). The elements of the monitor unit(250) are described as follows. An optical signal conversion monitor module(260) converts the optical signal transmitted from the optical signal conversion card module(230) into a digital signal and outputs the digital signal to a monitor control unit(270). Also, the optical signal conversion monitor module(260) converts the digital signal transmitted from the monitor control unit(270) into an optical signal and outputs the optical signal to the card(200). The monitor control unit(270) controls a data transmission between the monitor module(260) and a VGA control unit(280). The VGA control unit(280) displays data transmitted from the monitor control unit(270) on a screen.

Abstract translation: 目的：提供一种用于光模块匹配的总线接口装置及其方法，以克服由于光模块接口的数字信号和光信号之间的转换而引起的延迟时间，该延迟时间通过延迟信号的驱动 在通过总线上的光模块接口为光模块接口写入数据的情况下允许使用数据。 构成：连接到外围组件互连（PCI）的图形数据发送/接收卡（200）安装在PC的PCI插槽上。 图形数据发送/接收卡（200）具有用于在PC的CPU与通过光缆（240）发送/接收图形数据的监视器单元（250）之间交换数据的功能。 卡（200）的元件如下所述。 桥接单元（210）处理用于将作为PC的系统总线的PCI总线连接到监视器单元（250）的接口。 卡控制单元（220）控制桥单元（210）和光信号转换卡模块（230）之间的数据传输。 光信号转换卡模块（230）将从卡控制单元（220）发送的数字信号转换为光信号，并将该光信号输出到监视器单元（250）。 此外，光信号转换卡模块（230）将从监视器单元（250）发送的光信号转换为数字信号，并将数字信号输出到卡控制单元（220）。 监视器单元（250）的元件如下所述。 光信号转换监视器模块（260）将从光信号转换卡模块（230）发送的光信号转换为数字信号，并将数字信号输出到监视器控制单元（270）。 此外，光信号转换监视模块（260）将从监视器控制单元（270）发送的数字信号转换为光信号，并将光信号输出到卡（200）。 监视器控制单元（270）控制监视器模块（260）和VGA控制单元（280）之间的数据传输。 VGA控制单元（280）在屏幕上显示从监视器控制单元（270）发送的数据。

公开(公告)号：KR1020010017501A

公开(公告)日：2001-03-05

申请号：KR1019990033051

申请日：1999-08-12

Applicant: 삼성전자주식회사

Inventor： 권철 ,  임재민

IPC: H04N7/20

CPC classification number: H04N5/4401 ,  H04N7/015 ,  H04N21/41

Abstract: PURPOSE: An interface device of a digital broadcasting receiving card is provided to form a digital broadcasting receiver as card form which can be installed in a computer. The digital broadcasting receiving card can communicates with a PCI controller which controls input/output of data through PCI bus. CONSTITUTION: An interface part(116) comprises many ports. A PCI controller interface port(117) is for interface with a PCI controller(115). An interrupter port(118) generates interrupt signal. An IIC controlling part(119) controls communication line of IIC mode. A buffer controlling port(120) controls a buffer. A GP I/O(general purpose input/output) port(121) controls each part of a digital broadcasting receiving card(100). A chip selecting port(122) selects chips. A TS(transport stream)-demultiplexer controlling port(123) controls a TS-demultiplexer(109). A graphic processing part controlling port(124) controls a graphic processing part(114).

Abstract translation: 目的：提供数字广播接收卡的接口装置，以形成可安装在计算机中的卡形式的数字广播接收机。 数字广播接收卡可与通过PCI总线控制数据输入/输出的PCI控制器进行通信。 构成：接口部分（116）包括许多端口。 PCI控制器接口端口（117）用于与PCI控制器（115）的接口。 中断端口（118）产生中断信号。 IIC控制部（119）控制IIC模式的通信线。 缓冲器控制端口（120）控制缓冲器。 GP I / O（通用输入/输出）端口（121）控制数字广播接收卡（100）的每个部分。 芯片选择端口（122）选择芯片。 TS（传输流） - 多路分解器控制端口（123）控制TS解复用器（109）。 图形处理部分控​​制端口（124）控制图形处理部分（114）。

公开(公告)号：KR1020010017500A

公开(公告)日：2001-03-05

申请号：KR1019990033050

申请日：1999-08-12

Applicant: 삼성전자주식회사

Inventor： 임재민 ,  권철 ,  서재유

IPC: H04N7/20

CPC classification number: H04N5/4401 ,  H04N7/015 ,  H04N21/41

Abstract: PURPOSE: A digital broadcasting reception card for a computer is provided so that a user can watch a digital broadcasting at a low cost, by installing a digital broadcasting receiver to a computer in the form of a card. CONSTITUTION: A tuner(104) tunes a channel selected by the user among the digital broadcasting signals of the respective channels. An intermediate frequency amplifying unit(105) filters an intermediate frequency band of the analog type digital broadcasting signal tuned by the tuner(104), and amplifies the filtered signal in an appropriate magnitude. A first A/D converter(106) converts the amplified broadcasting signal into a digital signal. A signal restoring unit restores an error of the digital broadcasting signal converted in the first A/D converter(106). A demultiplexer(109) divides the digital broadcasting signal into a video signal, audio signal, text signal and other information. A video signal processing unit(112) processes the video signal. An audio signal processing unit(110) processes the audio signal. A bus interface unit(116) interfaces a power bus, data bus and computer(200). Accordingly, a general receiver for receiving the digital broadcasting is formed in a card type, and thus installed to the computer. As a result, the user can watch the digital broadcasting at a low cost.

Abstract translation: 目的：提供一种用于计算机的数字广播接收卡，以便用户可以以低成本观看数字广播，通过将数字广播接收机以卡形式安装到计算机。 构成：调谐器（104）调谐用户在相应频道的数字广播信号中选择的频道。 中频放大单元（105）对由调谐器（104）调谐的模拟型数字广播信号的中频带进行滤波，并以适当的大小放大经滤波的信号。 第一A / D转换器（106）将放大的广播信号转换成数字信号。 信号恢复单元恢复在第一A / D转换器（106）中转换的数字广播信号的错误。 解复用器（109）将数字广播信号划分为视频信号，音频信号，文本信号和其他信息。 视频信号处理单元（112）处理视频信号。 音频信号处理单元（110）处理音频信号。 总线接口单元（116）连接电力总线，数据总线和计算机（200）。 因此，用于接收数字广播的通用接收机是以卡片形式形成的，因此被安装到计算机上。 结果，用户可以以低成本观看数字广播。

公开(公告)号：KR1020000060341A

公开(公告)日：2000-10-16

申请号：KR1019990008558

申请日：1999-03-15

Applicant: 삼성전자주식회사

Inventor： 임재민

IPC: G01R31/26 ,  H01L21/66

Abstract: PURPOSE: An Apparatus for debugging a high-speed circuit is provided to make easy debugging by serially connecting a resistor and connector to a signal line of a high-speed component. CONSTITUTION: An Apparatus for debugging a high-speed circuit includes at least two high-speed circuits, a connector, a switching part, a testing connector, and a second terminal. The high-speed circuit(10,20) connects between the high-speed circuit components. The switching part has two terminals. The testing connector is connected to a first terminal among the two terminals of the switching part, and transmits a high-speed signal of the high-speed circuit to an external analyzer. The second terminal of the two terminals of the switching part is connected to the connector(40) with a stub length. Thereby, the apparatus for debugging a high-speed circuit makes easy debugging by serially connecting a resistor and connector to a signal line of a high-speed component.

Abstract translation: 目的：提供一种用于调试高速电路的设备，通过将电阻和连接器串行连接到高速分量的信号线进行简单的调试。 构成：用于调试高速电路的装置包括至少两个高速电路，连接器，开关部件，测试连接器和第二端子。 高速电路（10,20）连接在高速电路组件之间。 开关部分有两个端子。 测试连接器连接到开关部分的两个端子中的第一端子，并将高速电路的高速信号传输到外部分析器。 切换部分的两个端子的第二端子以短截线长度连接到连接器（40）。 因此，用于调试高速电路的装置通过将电阻器和连接器串行连接到高速分量的信号线来进行简单的调试。