公开(公告)号：KR1020050064107A

公开(公告)日：2005-06-29

申请号：KR1020030095389

申请日：2003-12-23

Applicant: 한국전자통신연구원

Inventor： 김영세 ,  이윤경 ,  이상우 ,  박영수 ,  전성익

IPC: H04L9/30

CPC classification number: H04L9/302

Abstract: 본 발명은 공개키 암호화 시스템에서 요구되는 파라메터들을 생성하기 위해 필요한 소수를 생성하는 방법에 관한 것으로서, 보다 상세하게는 공개키 암호화 시스템이 일반적으로 구비하고 있는 RSA 연산기를 이용하여 소수를 생성하는 방법 및 이에 적합한 장치에 관한 것이다.
본 발명에 따른 소수 생성 방법은 모듈라 지수승 연산기를 구비하는 공개키 암호화에 기반한 시스템에서 암호화에 필요한 파라메터인 소수를 발생하는 방법에 있어서, 임의의 난수 R을 발생하는 난수 발생 과정; 및 임의의 난수 R와 기지의 소수 p를 이용하여 임의의 소수 n을 발생하는 소수 생성 과정; 및 포클링턴(Pooklington)의 소수 판정법에 의해 상기 임의의 소수가 확정적 소수인지를 판정하는 소수 판정 과정을 포함하는 것을 특징으로 한다.
본 발명에 따른 소수 생성 방법 및 장치는 공개키 암호화 시스템에 존재하는 하드웨어 자원에 단지 일련의 소프트웨어를 부가함으로써 소수 생성이 가능하게 되므로, 추가적인 하드웨어를 요구하지 않고 시스템 면적의 증가를 야기하지도 않으므로 스마트 카드와 같은 면적이 제한된 소형 임베디드 시스템에 매우 적합하다.

公开(公告)号：KR1020040033157A

公开(公告)日：2004-04-21

申请号：KR1020020062075

申请日：2002-10-11

Applicant: 한국전자통신연구원

Inventor： 박지만 ,  전용성 ,  주홍일 ,  박영수 ,  전성익 ,  정교일

IPC: H04B1/40

CPC classification number: G06K19/0723

Abstract: PURPOSE: An RFID(Radio Frequency Identification) and a method for operating the same are provided to configure a special logic circuit that processes signals to control the operations of an RFID. CONSTITUTION: An RFID comprises an antenna(100), an analog signal processing part(110), a digital signal processing part(120), and a logic operation part(130). The antenna(100) transmits and receives signals with an external devices. The analog signal processing part(110) converts an analog signal, received to the antenna(100), into a digital signal. Also the analog signal processing part(110) converts a digital signal to be transmitted to the external device into an analog signal and transmits it to the antenna(100). The digital signal processing part(120) receives a digital signal from the analog signal processing part(110), demodulates the received signal, and detects an SOF(Start Of Frame) signal and an EOF(End Of Frame) signal. The logic operation part(130) comprises a memory unit and a logic processing unit to process the data transmitted and received with the external device.

Abstract translation: 目的：提供RFID（射频识别）及其操作方法，以配置处理信号以控制RFID操作的特殊逻辑电路。 构成：RFID包括天线（100），模拟信号处理部分（110），数字信号处理部分（120）和逻辑运算部分（130）。 天线（100）利用外部设备发送和接收信号。 模拟信号处理部分（110）将接收到天线（100）的模拟信号转换为数字信号。 此外，模拟信号处理部分（110）将要发送到外部设备的数字信号转换成模拟信号并将其发送到天线（100）。 数字信号处理部（120）从模拟信号处理部（110）接收数字信号，对接收到的信号进行解调，并检测出SOF（起始帧）信号和EOF（帧结束）信号。 逻辑运算部分（130）包括存储器单元和逻辑处理单元，用于处理与外部设备发送和接收的数据。

公开(公告)号：KR100419485B1

公开(公告)日：2004-02-19

申请号：KR1020010044113

申请日：2001-07-23

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  최용제 ,  김호원 ,  박영수

IPC: G06K19/07

Abstract: PURPOSE: A power supply unit for an IC card and a method for controlling the same are provided to minimize an electric power consumption necessary for driving a system and perform a stable operation in an IC card system having an internal power source(battery). CONSTITUTION: An internal power source(110) supplies a power source of a predetermined level in the case that an internal circuit unit(200) of a card system is an operation mode or a waiting mode. A switching control circuit unit(120) receives a mode judgement signal from a mode judgement unit in the internal circuit unit(200) which judges whether the card system is an operation mode or a waiting mode, and supplies a switching control signal to the first switching unit(140) and the second switching unit(141) in accordance with the received mode judgement signal, respectively. That is, in the case that the card system is an operation mode, the switching control circuit unit(120) supplies a switching control signal to the first switching unit(140) for making the internal power source(110) be supplied to the internal circuit unit(200) and making the internal power source(110) be accumulated in an electric charge accumulating circuit unit(130). Also, the switching control circuit unit(120) supplies a switching control signal to the second switching unit(141) for making an electric charge be accumulated in an electric charge accumulating circuit unit(130).

Abstract translation: 目的：提供一种用于IC卡的供电单元及其控制方法，以使驱动系统所需的电力消耗最小化，并在具有内部电源（电池）的IC卡系统中执行稳定的操作。 构成：在卡系统的内部电路单元（200）是工作模式或等待模式的情况下，内部电源（110）提供预定电平的电源。 开关控制电路单元（120）从判定卡系统是工作模式还是等待模式的内部电路单元（200）中的模式判断单元接收模式判断信号，并将切换控制信号提供给第一 切换单元（140）和第二切换单元（141）分别根据接收到的模式判断信号进行切换。 也就是说，在卡系统是操作模式的情况下，切换控制电路单元（120）向第一切换单元（140）提供切换控制信号，以使内部电源（110）被提供给内部 （200），并使内部电源（110）蓄积在电荷蓄积电路部（130）中。 此外，切换控制电路单元（120）将切换控制信号提供给第二切换单元（141），以使电荷积聚在电荷积聚电路单元（130）中。

公开(公告)号：KR1020040000891A

公开(公告)日：2004-01-07

申请号：KR1020020035896

申请日：2002-06-26

Applicant: 한국전자통신연구원

Inventor： 이상우 ,  김영세 ,  조진만 ,  박지만 ,  박영수 ,  전성익

IPC: G06K17/00

Abstract: PURPOSE: A system and a method for collecting/managing SAM(secure Application Module) for a non-contact typed electronic cash reader are provided to change SAM information using a SAM management card, not need to separate the SAM from a terminal. CONSTITUTION: An SAM(100) stores a key-set, executes mutual authentication among IC cards for the differential non-contact typed electronic cash. An SAM managing card(300) changes the SAM information. A collecting card(400) collects accumulated trading information. A reader(200) recognizes the SAM managing card(300) and the collecting card(400). The reader(200) communicates with the SAM managing card(300) and the collecting card(400).

Abstract translation: 目的：提供用于收集/管理非接触式电子现金阅读器的SAM（安全应用模块）的系统和方法，以使用SAM管理卡更改SAM信息，而不需要将SAM与终端分离。 构成：SAM（100）存储密钥集，在差分非接触型电子现金的IC卡之间执行相互认证。 SAM管理卡（300）更改SAM信息。 收款卡（400）收集积累的交易信息。 读取器（200）识别SAM管理卡（300）和收集卡（400）。 读取器（200）与SAM管理卡（300）和收集卡（400）通信。

公开(公告)号：KR100406138B1

公开(公告)日：2003-11-14

申请号：KR1020010074631

申请日：2001-11-28

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  박영수

IPC: H04L9/14

Abstract: PURPOSE: An NTRU encoding/decoding device is provided to perform efficiently an NTRU encoding/decoding process by improving a structure of the NTRU encoding/decoding device. CONSTITUTION: The first storage portion(12) stores an input message for NTRU encoding and a secret key for NTRU decoding. The second storage portion(13) stores an input value of a polynomial expression using p as a modular value of a coefficient. The third storage portion(14) stores an input value of a polynomial expression using q as a modular value of a coefficient. An NTRU calculation portion(16) performs an NTRU cryptographic calculation and a decoding calculation for values of the first to the third storage portions. The fourth storage portion(17) stores an output value of the NTRU calculation portion. An output selection portion(18) determines an output operation of the fourth storage portion. A modular calculation portion(19) performs a modular calculation process for an output value of the output selection portion. An NTRU control portion(15) controls each register and the NTRU calculation portion.

Abstract translation: 目的：提供一种NTRU编码/解码设备，通过改进NTRU编码/解码设备的结构来有效地执行NTRU编码/解码处理。 构成：第一存储部分（12）存储用于NTRU编码的输入消息和用于NTRU解码的秘密密钥。 第二存储部分（13）存储使用p作为系数的模值的多项式的输入值。 第三存储部分（14）存储使用q作为系数的模值的多项式的输入值。 NTRU计算部分（16）对第一至第三存储部分的值执行NTRU密码计算和解码计算。 第四存储部分（17）存储NTRU计算部分的输出值。 输出选择部分（18）确定第四存储部分的输出操作。 模块计算部分（19）对输出选择部分的输出值执行模块计算处理。 NTRU控制部分（15）控制每个寄存器和NTRU计算部分。

公开(公告)号：KR1020030048243A

公开(公告)日：2003-06-19

申请号：KR1020010078127

申请日：2001-12-11

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  김호원 ,  최용제 ,  박영수 ,  정교일

IPC: G06F7/44

Abstract: PURPOSE: A device for a modular multiplication is provided to execute a modular multiplication at high speed by repeating a bit multiplication and executing a modular multiplication of data more than a specific bit, thereby reducing a circuit area of a modular multiplication device, and a reducing memory accessing times using a register for storing a mid-point. CONSTITUTION: A memory(160) stores data for executing a modular multiplication of information. A processor requests the modular multiplication and loads/uses the multiplication results from the memory(160). A register(230) receives data for a modular multiplication from the memory(160), stores the data, and stores a mid-point being generated during the modular multiplication. A modular circuit(240) repeats a bit multiplication calculation, executes a modular multiplication of data which are greater than a specific bit, and stores a mid-point in the register(230) and a result value in the memory(160). A reduction circuit(250) corrects the result value selectively in accordance with a comparison result of the result value and the modular value. A control circuit(220) outputs various kinds of control signals to the register(230), the modular circuit(240), and the reduction circuit(250), and controls the modular multiplication.

Abstract translation: 目的：提供一种用于模乘的装置，通过重复比特乘法和执行比特定比特数据的模数乘法，高速执行模乘法，从而减少了乘法装置的电路面积，并减少了 使用寄存器存储中点的存储器存取时间。 构成：存储器（160）存储用于执行信息的模数乘法的数据。 处理器请求模乘，并加载/使用来自存储器的乘法结果（160）。 寄存器（230）从存储器（160）接收用于模数乘法的数据，存储数据，并存储在模乘期间生成的中点。 模块化电路（240）重复位乘法计算，执行大于特定位的数据的模乘，并将寄存器（230）中的中点和结果值存储在存储器（160）中。 还原电路（250）根据结果值和模块值的比较结果有选择地校正结果值。 控制电路（220）向寄存器（230），模块电路（240）和还原电路（250）输出各种控制信号，并控制模乘。

公开(公告)号：KR1020030024100A

公开(公告)日：2003-03-26

申请号：KR1020010057083

申请日：2001-09-17

Applicant: 한국전자통신연구원

Inventor： 박지만 ,  전용성 ,  박영수 ,  정교일

IPC: G06F13/00

Abstract: PURPOSE: A smart card emulator and an emulation method thereof are provided to effectively develop a contact/non-contact smart card and a USB(Universal Serial Bus) card through the simple design modification of a hardware logic. CONSTITUTION: The smart card emulator includes a computer(100), a controlling block(202), two ports(204,208), the first memory block(206), the second memory block(210), a clock generating block(212), a signal processing block(214) and an interface block(216). The controlling block(202) performs entire control needed to perform the emulation of the smart card. The first memory block(206) stores a VHDL(VHSIC(Very High Speed IC) Hardware Description Language) code needed to design the hardware logic. The second memory block(210) comprises an SRAM reading and writing the contents according to the execution of the emulator, a ROM storing an OS(Operating System) program of the emulator and an EEPROM(Electronically Erasable Programmable ROM) storing various application programs. The signal processing block(214) is an FPGA(Field Programmable Gate Array) for realizing a user defined additional function module.

Abstract translation: 目的：提供智能卡仿真器及其仿真方法，通过硬件逻辑的简单设计修改来有效地开发接触/非接触智能卡和USB（通用串行总线）卡。 构成：智能卡仿真器包括计算机（100），控制块（202），两个端口（204,208），第一存储块（206），第二存储器块（210），时钟生成块（212） 信号处理块（214）和接口块（216）。 控制块（202）执行执行智能卡仿真所需的全部控制。 第一存储器块（206）存储设计硬件逻辑所需的VHDL（VHSIC（超高速IC）硬件描述语言）代码。 第二存储器块（210）包括根据仿真器的执行读取和写入内容的SRAM，存储仿真器的OS（操作系统）程序的ROM和存储各种应用程序的EEPROM（电可擦除可编程ROM）。 信号处理块（214）是用于实现用户定义的附加功能模块的FPGA（现场可编程门阵列）。

公开(公告)号：KR1020020013985A

公开(公告)日：2002-02-25

申请号：KR1020000046391

申请日：2000-08-10

Applicant: 한국전자통신연구원

Inventor： 박영수 ,  김호원

IPC: G06F13/00

Abstract: PURPOSE: An interface device for a general processor and a coprocessor for encryption process is provided to simply and efficiently interface the general processor and the coprocessor by decoding a control signal and address generated in the general processor to be used in the coprocessor, transmitting, and receiving data using a previously ready memory map. CONSTITUTION: A coprocessor controller(200) decodes data according to an encryption algorithm outputted from a general processor(100) and outputs a control signal to an encryption process coprocessor(300) and an external device. A 3-state buffer(400) selectively provides output data of the general processor(100) to the external device, the encryption process coprocessor(300), or a multiplexer(500). The multiplexer(500) receives an output signal of the 3-state buffer(400) and a state signal from the encryption process coprocessor(300) and provides the received output signal and state signal to the general processor(100). The general processor(100) transmits and receives data with the external device and the encryption process coprocessor(300) using a previously ready memory map.

Abstract translation: 目的：提供用于通用处理器和用于加密处理的协处理器的接口设备，用于通过对通用处理器中生成的控制信号和地址进行解码来简单有效地对通用处理器和协处理器进行接口，以在协处理器中使用，发送和 使用先前准备好的存储器映射接收数据。 构成：协处理器控制器（200）根据从通用处理器（100）输出的加密算法解码数据，并将控制信号输出到加密处理协处理器（300）和外部设备。 3状态缓冲器（400）有选择地将通用处理器（100）的输出数据提供给外部设备，加密处理协处理器（300）或复用器（500）。 多路复用器（500）接收3状态缓冲器（400）的输出信号和来自加密处理协处理器（300）的状态信号，并将所接收的输出信号和状态信号提供给通用处理器（100）。 一般处理器（100）使用预先准备好的存储器映射与外部设备和加密处理协处理器（300）发送和接收数据。

公开(公告)号：KR100155322B1

公开(公告)日：1998-12-15

申请号：KR1019950042070

申请日：1995-11-17

Applicant: 한국전자통신연구원

Inventor： 박영수 ,  조한진

IPC: H03K19/00 ,  H03K19/0175

Abstract: 본 발명은 집적회로에서 인버팅 기능을 갖는 프로그램이 가능한 양방향성 버퍼에 관한 것으로서, 소정 갯수로 입력되는 제어신호의 논리레벨에 따라 스위칭하는 스위칭 수단과, 스위칭 수단에 의해 출력된 입력신호를 인버팅하여 양방향으로 출력하는 인버팅 수단으로 구성되어 임계경로의 지연시간을 줄일 수 있고 칩의 성능을 향상시킬 수가 있는 것이다.

公开(公告)号：KR1019980043589A

公开(公告)日：1998-09-05

申请号：KR1019960061512

申请日：1996-12-04

Applicant: 한국전자통신연구원

Inventor： 박영수 ,  조한진

IPC: H03K23/00

Abstract: 본 발명은 적은 수의 트랜지스터를 사용하여 두 개의 클럭 신호 모서리 모두에서 동작하고, 전력 소모를 줄이며 시스템의 속도를 증가시킬 수 있는 동적 디형 듀얼 모서리 트리거 플립플롭 회로에 관한 것이다.