公开(公告)号：KR1020030054296A

公开(公告)日：2003-07-02

申请号：KR1020010084437

申请日：2001-12-24

Applicant: 한국전자통신연구원

Inventor： 손동환 ,  유찬수 ,  김흥남

IPC: H04N19/156 ,  H04N19/42

CPC classification number: H04N19/42 ,  H04N19/61

Abstract: PURPOSE: An MPEG decoding system and method using a variation in an operation frequency and drive voltage is provided to change a drive frequency and operation voltage of a processor to support real-time MPEG decoding. CONSTITUTION: An MPEG decoding system using a variation in an operation frequency and drive voltage includes an interrupt generator(100), an operation frequency and drive voltage setting unit(200), and a decoder(300). The interrupt generator generates an interrupt. The operation frequency and drive voltage setting unit sets an operation frequency and drive voltage of a processor according to a difference between the number of processing frames and the number of set frames, corresponding to the interrupt generated by the interrupt generator, to maintain real-time decoding. The decoder decodes frames until the next interrupt is generator.

Abstract translation: 目的：提供使用操作频率和驱动电压变化的MPEG解码系统和方法来改变处理器的驱动频率和操作电压以支持实时MPEG解码。 构成：使用操作频率和驱动电压变化的MPEG解码系统包括中断发生器（100），操作频率和驱动电压设定单元（200）以及解码器（300）。 中断发生器产生一个中断。 操作频率和驱动电压设定单元根据处理帧的数量和与由中断发生器产生的中断相对应的设定帧数之间的差设定处理器的操作频率和驱动电压，以保持实时 解码。 解码器解码帧直到下一个中​​断为发生器。