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    System for link management between multiple communication chips
    21.
    发明授权
    System for link management between multiple communication chips 有权

    公开(公告)号：US11176069B2

    公开(公告)日：2021-11-16

    申请号：US16885889

    申请日：2020-05-28

    Applicant: Apple Inc.

    Inventor： Helena Deirdre O'Shea ,  Camille Chen ,  Vijay Kumar Ramamurthi ,  Alon Paycher ,  Matthias Sauer ,  Bernd W. Adler

    IPC: G06F13/362 ,  G06F13/24 ,  G06F11/34 ,  G06F11/30 ,  G06F13/28

    Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

    BUS PROTOCOL FOR MULTIPLE CHIPSETS
    22.
    发明申请
    BUS PROTOCOL FOR MULTIPLE CHIPSETS 有权

    公开(公告)号：US20210318977A1

    公开(公告)日：2021-10-14

    申请号：US17357156

    申请日：2021-06-24

    Applicant: Apple Inc.

    Inventor： Farouk Belghoul ,  Paul V. Flynn ,  Tideya Kella ,  Vijay Kumar Ramamurthi

    IPC: G06F13/40 ,  H04L29/08 ,  H04L12/40

    Abstract: Circuits, methods, and apparatus that can allow chipsets in an electronic device to share information such that they can more efficiently utilize resources that are available in the electronic device. One example can provide a bus that is shared by three or more chipsets in an electronic device. This shared bus can be used by the chipsets in the electronic device to communicate and negotiate for the utilization of resources of the electronic device.

    Paging mechanisms for link-budget-limited user devices
    23.
    发明授权
    Paging mechanisms for link-budget-limited user devices 有权

    公开(公告)号：US10264545B2

    公开(公告)日：2019-04-16

    申请号：US15414754

    申请日：2017-01-25

    Applicant: Apple Inc.

    Inventor： Li Su ,  Sami M. Almalfouh ,  Venkateswara Rao Manepalli ,  Srinivas Burugupalli ,  Srinivasan Nimmala ,  Vijay Kumar Ramamurthi ,  Stephan V. Schell

    IPC: H04W68/00 ,  H04W64/00 ,  H04W68/02 ,  H04W72/04 ,  H04W76/28

    Abstract: Various mechanisms for paging link-budget-limited (LBL) devices are disclosed, including: (1) transmitting paging message with non-conventional paging identifier; (2) transmitting paging message(s) with increased power; (3) repeating transmission of paging message to support combining at receiver. Various mechanisms for UE device to signal LBL status are disclosed, including, transmitting status flag or special value of DRX cycle to network node as part of tracking area update and/or attach request. The network node informs a base station of the device's LBL status as part of a paging message. (The network node may, e.g., assign an S-RNTI to the LBL device from a reserved subset of S-RNTI space.) The base station invokes a paging enhancement mechanism when paging an LBL device. Alternatively, the base station may page UE devices without knowledge of LBL status, e.g., by counting paging attempts for a given UE, and boosting power after the Nth paging attempt.

    Paging Mechanisms for Link-Budget-Limited User Devices
    26.
    发明申请
    Paging Mechanisms for Link-Budget-Limited User Devices 审中-公开

    公开(公告)号：US20170135067A1

    公开(公告)日：2017-05-11

    申请号：US15414754

    申请日：2017-01-25

    Applicant: Apple Inc.

    Inventor： Li Su ,  Sami M. Almalfouh ,  Venkateswara Rao Manepalli ,  Srinivas Burugupalli ,  Srinivasan Nimmala ,  Vijay Kumar Ramamurthi ,  Stephan V. Schell

    IPC: H04W68/02 ,  H04W64/00

    CPC classification number: H04W68/005 ,  H04W64/003 ,  H04W68/02 ,  H04W72/0446 ,  H04W72/048 ,  H04W76/28

    Abstract: Various mechanisms for paging link-budget-limited (LBL) devices are disclosed, including: (1) transmitting paging message with non-conventional paging identifier; (2) transmitting paging message(s) with increased power; (3) repeating transmission of paging message to support combining at receiver. Various mechanisms for UE device to signal LBL status are disclosed, including, transmitting status flag or special value of DRX cycle to network node as part of tracking area update and/or attach request. The network node informs a base station of the device's LBL status as part of a paging message. (The network node may, e.g., assign an S-RNTI to the LBL device from a reserved subset of S-RNTI space.) The base station invokes a paging enhancement mechanism when paging an LBL device. Alternatively, the base station may page UE devices without knowledge of LBL status, e.g., by counting paging attempts for a given UE, and boosting power after the Nth paging attempt.

    SYSTEM FOR LINK MANAGEMENT BETWEEN MULTIPLE COMMUNICATION CHIPS
    30.
    发明申请
    SYSTEM FOR LINK MANAGEMENT BETWEEN MULTIPLE COMMUNICATION CHIPS 有权

    公开(公告)号：US20220035757A1

    公开(公告)日：2022-02-03

    申请号：US17500325

    申请日：2021-10-13

    Applicant: Apple Inc.

    Inventor： Helena Deirdre O'Shea ,  Camille Chen ,  Vijay Kumar Ramamurthi ,  Alon Paycher ,  Matthias Sauer ,  Bernd W. Adler

    IPC: G06F13/362 ,  G06F13/24 ,  G06F11/34 ,  G06F11/30 ,  G06F13/28

    Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.

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