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    25.
    发明专利
    未知

    公开(公告)号：SE320720B

    公开(公告)日：1970-02-16

    申请号：SE1347466

    申请日：1966-10-06

    Applicant: ASEA AB

    Inventor： JAAKSOO L ,  JOHANSSON A ,  STANGE W

    IPC: H01F27/40 ,  H01F38/28 ,  H01F38/30 ,  H01R13/703 ,  G01R1/04

    Abstract: 1,197,299. Electric couplings. ALLMANNA SVENSKA ELEKTRISKA A.B. 13 Nov., 1967, No. 51431/67. Heading H2E. [Also in Division H1] Contact jacks 9 connected via cables 13 to the secondary circuit of a transformer are short circuited when apparatus such as plug-in relay 20 is disconnected by a conductive body 4 spring loaded within aperture 3 in insulating body 2. The lengths of pin 22 on relay 20 and guide pin 14 on body 4 are such that on insertion plugs 21 make good connection with contacts 9 before body 4 is pressed so far to the right that the short-circuit connection is broken.

    26.
    发明专利
    未知

    公开(公告)号：SE303537B

    公开(公告)日：1968-09-02

    申请号：SE307263

    申请日：1963-03-21

    Applicant: ASEA AB

    Inventor： JOHANSSON A

    IPC: H02H3/247 ,  H02H7/26 ,  H01H83/12

    Abstract: 1,053,029. Converting. ALLMANNA SVEN- 8KA ELEKTRISKA A.B. March 20, 1964 [March 21, 1963], No. 11833/64. Heading H2F. Protection against earth faults on the D.C. line in a H.V.D.C.P.T. system is effected by means which distinguish between low line voltage due to earth faults and low line voltage due to converter valve faults, and is based on the observation that with line faults oscillations in the line voltage are quickly damped out and the voltage soon falls to a constant low value, and with valve faults high voltage oscillations at A.C. network frequency occur. In brief, output at 30 (which effects a reduction to zero of the rectifier station voltage) is dependent on the conduction of a thyristor 4. Faults are detected at 1 and 5 and the faults at 1 provide pulses which are time delayed by 8 and 9. If the line voltage has been low for the latter part of this time (line fault conditions), the output from 5 is such as to enable the pulse from line to be passed to the thyristor 4. If, however, the voltage has risen during the latter part of this time (valve fault conditions) the pulse is not passed. In greater detail line voltage at 20 is applied in box 5 to a potentiometer 57, 58 whose junction is connected through a Zener diode 53 to a normally conducting unijunction transistor 54. If when the line voltage falls, the Zener voltage is not exceeded current is passed via diode 59 to hold on the thyristor 6. If the line voltage now rises this current ceases. (A similar arrangement 51, 52, 55, 56 in box 5 operates on an even lower line voltage and acts directly to hold on thyristor 4.) The line voltage is also detected across a unijunction transistor 11 and when it falls a capacitor 14 discharges through the UJT 11. (Alternatively a time derivative of the line voltage derived from the box 7 may be used, in which case the switch 15 is in its right-hand position.) Output from the UJT 11 is applied to a transistor 85, and a pulse is obtained via winding 84 and diode 85 1 to start the thyristor 6. A pulse of current then flows through 85 1 , diode 61 and thyristor 6. The duration of this pulse, limited by the saturation of the transformer core, covers the period of the high-frequency quickly-damped oscillations which occur with the line faults. If at the end of this pulse the line voltage is low the thyristor 6 will now be held on by current through 59. At the end of the pulse an output from winding 84 is obtained and further delayed by a period corresponding to the A.C. frequency in circuit 9 which includes a further UJT 91, providing an output at 93. Now, if during the whole of this second period the line voltage has remained low (line fault conditions) the thyristor 6 will have been held on all this time and the output from 93 will be able to pass through it via the winding 65. In so doing a pulse is induced in winding 66 to fire thyristor 4, and give an output at 30. If on the other hand the fault is a valve fault, the line voltage will rise during this second period. rendering thyristor 6 non-conducting. In this case no signal passes from 93 and no output at 30 obtains. In the event of serious faults giving rise to large voltage time derivatives, the delay circuit is by-passed, output from the circuit 7 being passed to circuit 10 via diode 75 and thence to fire thyristor 4. Thyristor 4 is in a circuit 3, similar to circuit 1. and having a load resistor 32. The Specification discloses (Fig. 2, not shown) an arrangement connected to the terminal 30 which effects repeated blocking and unblocking of the converter station, permanent blocking being effected-after several repetitions.

    EARTH FAULT PROTECTION MEANS FOR DIRECT CURRENT TRANSMISSION SYSTEMS
    27.
    发明专利
    EARTH FAULT PROTECTION MEANS FOR DIRECT CURRENT TRANSMISSION SYSTEMS 未知

    公开(公告)号：GB1053029A

    公开(公告)日：1966-12-30

    申请号：GB1183364

    申请日：1964-03-20

    Applicant: ASEA AB

    Inventor： JOHANSSON A

    IPC: H02H3/247 ,  H02H7/26

    Abstract: 1,053,029. Converting. ALLMANNA SVEN- 8KA ELEKTRISKA A.B. March 20, 1964 [March 21, 1963], No. 11833/64. Heading H2F. Protection against earth faults on the D.C. line in a H.V.D.C.P.T. system is effected by means which distinguish between low line voltage due to earth faults and low line voltage due to converter valve faults, and is based on the observation that with line faults oscillations in the line voltage are quickly damped out and the voltage soon falls to a constant low value, and with valve faults high voltage oscillations at A.C. network frequency occur. In brief, output at 30 (which effects a reduction to zero of the rectifier station voltage) is dependent on the conduction of a thyristor 4. Faults are detected at 1 and 5 and the faults at 1 provide pulses which are time delayed by 8 and 9. If the line voltage has been low for the latter part of this time (line fault conditions), the output from 5 is such as to enable the pulse from line to be passed to the thyristor 4. If, however, the voltage has risen during the latter part of this time (valve fault conditions) the pulse is not passed. In greater detail line voltage at 20 is applied in box 5 to a potentiometer 57, 58 whose junction is connected through a Zener diode 53 to a normally conducting unijunction transistor 54. If when the line voltage falls, the Zener voltage is not exceeded current is passed via diode 59 to hold on the thyristor 6. If the line voltage now rises this current ceases. (A similar arrangement 51, 52, 55, 56 in box 5 operates on an even lower line voltage and acts directly to hold on thyristor 4.) The line voltage is also detected across a unijunction transistor 11 and when it falls a capacitor 14 discharges through the UJT 11. (Alternatively a time derivative of the line voltage derived from the box 7 may be used, in which case the switch 15 is in its right-hand position.) Output from the UJT 11 is applied to a transistor 85, and a pulse is obtained via winding 84 and diode 85 1 to start the thyristor 6. A pulse of current then flows through 85 1 , diode 61 and thyristor 6. The duration of this pulse, limited by the saturation of the transformer core, covers the period of the high-frequency quickly-damped oscillations which occur with the line faults. If at the end of this pulse the line voltage is low the thyristor 6 will now be held on by current through 59. At the end of the pulse an output from winding 84 is obtained and further delayed by a period corresponding to the A.C. frequency in circuit 9 which includes a further UJT 91, providing an output at 93. Now, if during the whole of this second period the line voltage has remained low (line fault conditions) the thyristor 6 will have been held on all this time and the output from 93 will be able to pass through it via the winding 65. In so doing a pulse is induced in winding 66 to fire thyristor 4, and give an output at 30. If on the other hand the fault is a valve fault, the line voltage will rise during this second period. rendering thyristor 6 non-conducting. In this case no signal passes from 93 and no output at 30 obtains. In the event of serious faults giving rise to large voltage time derivatives, the delay circuit is by-passed, output from the circuit 7 being passed to circuit 10 via diode 75 and thence to fire thyristor 4. Thyristor 4 is in a circuit 3, similar to circuit 1. and having a load resistor 32. The Specification discloses (Fig. 2, not shown) an arrangement connected to the terminal 30 which effects repeated blocking and unblocking of the converter station, permanent blocking being effected-after several repetitions.

    CLAMPING DEVICE
    28.
    发明专利
    CLAMPING DEVICE 未知

    公开(公告)号：ZA822468B

    公开(公告)日：1983-02-23

    申请号：ZA822468

    申请日：1982-04-13

    Applicant: ASEA AB

    Inventor： JOHANSSON A ,  JOHANSSON L

    IPC: B29C61/02 ,  F16B2/04 ,  F16B2/14 ,  F16B4/00 ,  H01F27/30

    Abstract: A wedging device comprises at least two bodies which are movable in relation to each other, namely a first body having two diverging surfaces and a second body which is displaceable relative to the first body along one of its diverging surfaces. A heat-shrinkable casing, made for example from a tape, sheet or film of polymeric material, is arranged around the movable bodies of the device. When the device is heated, the casing shrinks, causing relative displacement between the first and second bodies and a consequent change in the outer dimensions of the device.

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