公开(公告)号：EP1036407A1

公开(公告)日：2000-09-20

申请号：EP98957470.2

申请日：1998-11-02

Applicant: ASM America, Inc.

Inventor： VAN BILSEN, Franciscus, B., M. ,  LAYTON, Jason, Matthew ,  RAAIJMAKERS, Ivo

IPC: H01L21/00

CPC classification number: C30B29/06 ,  C30B25/10

Abstract: A method is provided for treating wafers (16) on a low mass support (18). The method includes mounting a temperature sensor (28) in proximity to the wafer (16), which is supported on the low mass support (18), such that the sensor (28) is only loosely thermally coupled to the wafer (16). A temperature controller (80) is programmed to critically tune the wafer temperature in a temperature ramp, though the controller directly controls the sensor temperature. A wafer treatment, such as epitaxial silicon deposition, is started before the sensor temperature has stabilized. Accordingly, significant time is saved for the treatment process, and wafer throughput improved.

Abstract translation: 提供了用于在低质量支撑件（18）上处理晶片（16）的方法。 该方法包括将温度传感器（28）安装在支撑在低质量支撑件（18）上的晶片（16）附近，使得传感器（28）仅松散地热耦合到晶片（16）。 虽然控制器直接控制传感器温度，但是温度控制器（80）被编程为临界地调整温度斜坡中的晶片温度。 在传感器温度稳定之前开始晶片处理，例如外延硅沉积。 因此，为处理过程节省了大量时间，并且提高了晶圆生产量。

公开(公告)号：EP1502285A2

公开(公告)日：2005-02-02

申请号：EP03728753.9

申请日：2003-05-07

Applicant: ASM America, Inc.

Inventor： WERKHOVEN, Chris ,  RAAIJMAKERS, Ivo ,  ARENA, Chantal

IPC: H01L21/00

CPC classification number: H01L21/31662 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3141 ,  H01L21/7624 ,  H01L21/76262

Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.

公开(公告)号：EP1044291B1

公开(公告)日：2003-04-02

申请号：EP99901394.9

申请日：1999-01-08

Applicant: ASM America, Inc.

Inventor： FERRO, Armand ,  RAAIJMAKERS, Ivo ,  FOSTER, Derrick

IPC: C30B25/02 ,  C30B29/06 ,  C23C16/02 ,  H01L21/205 ,  C30B33/00 ,  H01L21/28

CPC classification number: C30B29/06 ,  C23C16/4405 ,  C23C16/481 ,  C30B25/02 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28017 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/31662 ,  H01L29/66651

公开(公告)号：EP1036406B1

公开(公告)日：2003-04-02

申请号：EP98956476.0

申请日：1998-11-02

Applicant: ASM America, Inc.

Inventor： GOODMAN, Matthew, G. ,  RAAIJMAKERS, Ivo ,  JACOBS, Loren, R. ,  VAN BILSEN, Franciscus, B., M. ,  MEYER, Michael, J. ,  BARRETT, Eric, Alan

IPC: H01L21/00

CPC classification number: H01L21/68735 ,  C23C16/4581 ,  C23C16/4585 ,  C23C16/481 ,  H01L21/68721 ,  H01L21/68728 ,  H01L21/68785

公开(公告)号：EP1266054A2

公开(公告)日：2002-12-18

申请号：EP01918295.5

申请日：2001-03-02

Applicant: ASM America, Inc.

Inventor： WERKHOVEN, Christiaan, J. ,  RAAIJMAKERS, Ivo ,  HAUKKA, Suvi, P.

IPC: C30B25/14 ,  C23C16/44 ,  H01L21/205

CPC classification number: H01L21/28185 ,  C23C16/029 ,  C23C16/34 ,  C23C16/401 ,  C23C16/403 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45534 ,  C30B25/14 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/3185 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24942 ,  Y10T428/2495 ,  H01L2924/00

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles (301) or (450, 455, 460, 470) including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources (306 or 460) are introduced during the cyclical process. A graded gate dielectric (72) is thereby provided, even for extremely thin layers. The gate dielectric (72) as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric (72) can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (432) (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses (460) can gradually increase in frequency, forming a graded transition region (434), until pure copper (436) is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces.

公开(公告)号：EP1216106A1

公开(公告)日：2002-06-26

申请号：EP00963326.4

申请日：2000-09-08

Applicant: ASM America, Inc.

Inventor： RAAIJMAKERS, Ivo

IPC: B05C11/00 ,  H05H1/10

CPC classification number: C23C16/45544 ,  C23C16/452 ,  C23C16/45521 ,  C23C16/45536 ,  C23C16/45542 ,  C30B25/14 ,  C30B29/38 ,  H01J37/3244 ,  Y10T117/10

Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas (C, D) delivery of sequential pulses of reactants (A, B) to the substrate surfaces. (5) At least one of the reactants (A, B) comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas (4, 13) for reaction at a substrate surfaces. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants (A, B) in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface (5).

公开(公告)号：EP1098830B1

公开(公告)日：2006-12-13

申请号：EP99933854.4

申请日：1999-07-08

Applicant: ASM America, Inc.

Inventor： CARR, Paul, R. ,  JACOBSON, Paul, T. ,  KUSBEL, James, F. ,  ROUNDY, James, S. ,  AGGARWAL, Ravinder, K. ,  RAAIJMAKERS, Ivo ,  LENZ, Rod ,  RAJBHARTI, Nilesh

IPC: B65G49/07 ,  H01L21/00

CPC classification number: H01L21/68735 ,  H01L21/67346 ,  H01L21/67778 ,  H01L21/68721 ,  H01L21/68728 ,  H01L21/68764 ,  H01L21/68771 ,  Y10S414/137 ,  Y10S414/141

Abstract: Disclosed is a carrier (10) comprising three support elements (50) connected by an underlying frame (15). The periphery of a wafer (45) rests upon the support elements (50). Also disclosed is a wafer handler (25) with a plurality of arms (100). Spacers (85) space the carrier (10) above a base plate (90) associated with a station in a wafer handling area. An arm (100) slides beneath the frame (15) and between the spacers (85), but the handler (25) does not contact the wafer (45). A method of using the handler (25) and carrier (10) is provided where the handler (55) lifts and rotates the carrier (10) with the wafer (45) through various stations (112, 125, 126 and 130) in a wafer handling area (95). A control device (33) reduces the handler speed only at critical points of the processing cycle. The handler (55) is capable of moving a plurality of carriers (10) and wafers (45) simultaneously.

公开(公告)号：EP1604395A2

公开(公告)日：2005-12-14

申请号：EP04720379.9

申请日：2004-03-12

Applicant: ASM America, Inc.

Inventor： BRABANT, Paul, D. ,  ITALIANO, Joseph, P. ,  ARENA, Chantal, J. ,  TOMASINI, Pierre ,  RAAIJMAKERS, Ivo ,  BAUER, Matthias

IPC: H01L21/31 ,  H01L31/072 ,  C30B23/00 ,  C23C16/00

CPC classification number: C30B29/08 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing (305) to lower deposition temperatures (315) for Ge-containing layers, Si or Ge compounds are provided (310) to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers (110) result. Retrograded relaxed SiGe (115) is also provided between a relaxed, high Ge-content seed layer (110) and an overlying strained layer (120).

Abstract translation: 沉积外延膜的方法，例如外延Ge和SiGe膜。 在从高温处理（305）冷却至含Ge层的较低沉积温度（315）期间，向衬底提供（310）Si或Ge化合物。 产生光滑，薄且相对无缺陷的Ge或SiGe层（110）。 还在松弛的高Ge含量种子层（110）和上覆应变层（120）之间提供逆向弛豫SiGe（115）。

公开(公告)号：EP1340269A2

公开(公告)日：2003-09-03

申请号：EP01995245.6

申请日：2001-11-26

Applicant: ASM Microchemistry Oy ,  ASM America, Inc.

Inventor： HUJANEN, Juha ,  RAAIJMAKERS, Ivo

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/30

CPC classification number: H01F10/3231 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G11B5/3903 ,  G11B5/3909 ,  G11B2005/3996 ,  H01F10/3254 ,  H01F41/22 ,  H01F41/307 ,  H01L43/12

Abstract: Methods are provided for forming uniformly thin layers in magnetic devices. Atomic layer deposition (ALD) can produce layers that are uniformly thick on an atomic scale. Magnetic tunnel junction dielectrics, for example, can be provided with perfect uniformity in thickness of 4 monolayers or less. Furthermore, conductive layers, including magnetic 12, 16 and non-magnetic layers 14, can be provided by ALD without spiking and other non-uniformity problems. The disclosed methods include forming metal oxide layers by multiple cycles of ALD and subsequently reducing the oxides to metal. The oxides tend to maintain more stable interfaces during formation.

公开(公告)号：EP1116261A1

公开(公告)日：2001-07-18

申请号：EP99948071.8

申请日：1999-08-26

Applicant: ASM America, Inc.

Inventor： RAAIJMAKERS, Ivo

IPC: H01L21/00 ,  C23C16/56 ,  C30B31/12

CPC classification number: H01L21/67109 ,  C23C16/54 ,  C23C16/56 ,  C30B25/10

Abstract: Methods and apparatuses are provided for cooling semiconductor substrates prior to handling. In one embodiment, a substrate and support structure combination is lifted after high temperature processing to a cold wall of a thermal processing chamber, which acts as a heat sink. Conductive heat transfer across a small gap from the substrate to the heat sink speeds wafer cooling prior to handling the wafer (e.g., with a robot). In another embodiment, a separate plate is kept cool within a pocket during processing, and is moved close to the substrate and support after processing. In yet another embodiment, a cooling station between a processing chamber and a storage cassette includes two movable cold plates, which are movable to positions closely spaced on either side of the wafer.