Devices with displays having transparent openings and transition regions

    公开(公告)号:US12185616B1

    公开(公告)日:2024-12-31

    申请号:US17840472

    申请日:2022-06-14

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display and an optical sensor formed underneath the display. The display may have both a full pixel density region and a pixel removal region with a plurality of high-transmittance areas that overlap the optical sensor. To mitigate reflectance mismatch between the full pixel density region and the pixel removal region, the pixel removal region may include a transition region at one or more edges. In the transition region, one or more components may have a gradual density change between the full pixel density region and a central portion of the pixel removal region. Components that may have a changing density in the transition region include dummy thin-film transistor sub-pixels, dummy anodes, a cathode layer, and a touch sensor metal layer. The transition region may also include anodes that gradually change shape and/or size.

    GLOBAL NONLINEAR SCALER FOR MULTIPLE PIXEL GAMMA RESPONSE COMPENSATION

    公开(公告)号:US20240203332A1

    公开(公告)日:2024-06-20

    申请号:US18509592

    申请日:2023-11-15

    Applicant: Apple Inc.

    CPC classification number: G09G3/3208 G09G3/32 G09G2300/0828 G09G2320/0276

    Abstract: In a display characterized by regions with different pixel responses due, for example, to local pixel density variation, voltage-to-luminance matching may be non-universal. Therefore, in order to avoid visual artifacts that may hinder a desired visualization of displayed content, it may be advantageous to compensate the different gamma responses. In some cases, such as with electronic devices having a single pixel density across the display, optical calibration may be performed to determine voltage-to-luminance matching. However, in electronic devices with local pixel density variations, it may be disadvantageous to perform optical calibrations for each region with a different pixel density. Instead of using two distinct gamma curves which may include dedicated optical calibration, a global nonlinear scaler (GNLS) compensation may be applied. Embodiments may pertain to techniques for applying a per-channel and band-global gamma-to-voltage compensation to reduce or minimize a relative luminance error amongst different responses of display regions.

    Display-synchronized optical emitters and transceivers

    公开(公告)号:US11295664B2

    公开(公告)日:2022-04-05

    申请号:US16815875

    申请日:2020-03-11

    Applicant: Apple Inc.

    Abstract: In some embodiments, a device includes a light-emitting display, and an optical emitter positioned behind the light-emitting display. The optical emitter is configured to emit light through the light-emitting display. A processor is configured to synchronize a first illumination timing of the optical emitter and a second illumination timing of the light-emitting display. In some embodiments, a device includes an optical transceiver processor and a display processor. The display processor is configured to output timing information to a light-emitting display and to the optical transceiver processor, and the optical transceiver processor is configured to cause an optical transceiver to emit or receive light in synchronization with the timing information output by the display processor.

    Reducing Border Width Around a Hole in Display Active Area

    公开(公告)号:US20210305350A1

    公开(公告)日:2021-09-30

    申请号:US17145815

    申请日:2021-01-11

    Applicant: Apple Inc.

    Abstract: An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.

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