公开(公告)号：US07432160B2

公开(公告)日：2008-10-07

申请号：US11699301

申请日：2007-01-29

Applicant: Eun-Suk Cho ,  Chul Lee

Inventor： Eun-Suk Cho ,  Chul Lee

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

Abstract translation: 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

公开(公告)号：US20080084731A1

公开(公告)日：2008-04-10

申请号：US11896029

申请日：2007-08-29

Applicant: Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang ,  Makoto Yoshida

Inventor： Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang ,  Makoto Yoshida

IPC: G11C11/401 ,  H01L27/108

CPC classification number: G11C11/404 ,  G11C11/4076 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/7851

Abstract: A dynamic random access memory (DRAM) device may include: a semiconductor substrate including an active fin, an active region, and an isolation layer; one or more cell gate structures on a central portion of the active fin; one or more dummy gate structures on a peripheral portion of the active fin; one or more source/drain regions at an upper portion of the active fin adjacent to the one or more cell gate structures; a first insulating interlayer on the semiconductor substrate; a bit line structure electrically connected to the at least one source region; a second insulating interlayer on the first insulating interlayer; one or more capacitors electrically connected to the at least one drain region; a third insulating interlayer on the second insulating interlayer; and a wire connected to the active region and at least one of the one or more dummy gate structures.

Abstract translation: 动态随机存取存储器（DRAM）装置可以包括：半导体衬底，其包括有源鳍片，有源区域和隔离层; 有源鳍片的中心部分上的一个或多个单元栅极结构; 活动鳍片的周边部分上的一个或多个虚拟栅极结构; 在与所述一个或多个单元栅极结构相邻的所述有源鳍片的上部处的一个或多个源极/漏极区域; 半导体衬底上的第一绝缘中间层; 电连接到所述至少一个源极区的位线结构; 在所述第一绝缘中间层上的第二绝缘中间层; 电连接到所述至少一个漏极区的一个或多个电容器; 在所述第二绝缘中间层上的第三绝缘中间层; 以及连接到有源区域和所述一个或多个虚拟栅极结构中的至少一个的导线。

公开(公告)号：US20070298599A1

公开(公告)日：2007-12-27

申请号：US11804875

申请日：2007-05-21

Applicant: Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

Inventor： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

IPC: H01L21/8232

CPC classification number: H01L21/823412

Abstract: For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.

Abstract translation: 为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。 在第二有源区上形成第一导电层以形成模具结构。 在模具结构之间形成掩模结构。 使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。 在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

公开(公告)号：US20070184627A1

公开(公告)日：2007-08-09

申请号：US11699301

申请日：2007-01-29

Applicant: Eun-Suk Cho ,  Chul Lee

Inventor： Eun-Suk Cho ,  Chul Lee

IPC: H01L21/20

CPC classification number: H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

Abstract translation: 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

公开(公告)号：US20070152553A1

公开(公告)日：2007-07-05

申请号：US11639432

申请日：2006-12-15

Applicant: Jae Jun ,  Jin Kim ,  Yong Song ,  Deok Kim ,  Won Kim ,  Chul Lee ,  Hae Jung

Inventor： Jae Jun ,  Jin Kim ,  Yong Song ,  Deok Kim ,  Won Kim ,  Chul Lee ,  Hae Jung

IPC: H01J61/52 ,  H01J7/24 ,  H01J1/02 ,  H01K1/58

CPC classification number: H05K7/20963 ,  H01J2217/492

Abstract: A plasma display panel adapted to minimize noise/vibration as well as a heat generated therefrom. In the plasma display panel, a display panel displays a picture while a porous pad is provided behind the display panel to prevent the transfer of noise/vibration to an associated heat proof panel. When the PDP is mounted within a case, a second porous pad can be provided on an inner surface of the case opposite the display panel and adjacent to an associated printed circuit board for additional noise/vibration damping.

Abstract translation: 等离子体显示面板适于最小化噪音/振动以及由此产生的热量。 在等离子体显示面板中，显示面板显示图像，同时在显示面板后面设置多孔垫以防止噪声/振动传递到相关的防热面板。 当PDP安装在壳体内时，第二多孔垫可以设置在与显示面板相对的壳体的内表面上并且邻近相关的印刷电路板，用于额外的噪声/振动阻尼。

公开(公告)号：US20070082809A1

公开(公告)日：2007-04-12

申请号：US11427001

申请日：2006-06-28

Applicant: Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

Inventor： Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

IPC: B01J27/182 ,  B01J29/08 ,  B01J29/18 ,  B01J29/00 ,  B01J29/04

CPC classification number: B01J29/40 ,  B01J29/061 ,  B01J29/405 ,  B01J29/46 ,  B01J2229/12 ,  B01J2229/18 ,  C10G29/205 ,  C10G2400/20

Abstract: Disclosed are a hydrothermally stable porous molecular sieve catalyst and a preparation method thereof. The catalyst consists of a product obtained by the evaporation of water from a raw material mixture comprising a molecular sieve having a framework of Si—OH—Al—, a water-insoluble metal salt and a phosphate compound. The catalyst maintains its physical and chemical stabilities even in an atmosphere of high temperature and humidity. Accordingly, the catalyst shows excellent catalytic activity even when it is used in a severe process environment of high temperature and humidity in heterogeneous catalytic reactions, such as various oxidation/reduction reactions, including catalytic cracking reactions, isomerization reactions, alkylation reactions and esterification reactions.

Abstract translation: 公开了一种水热稳定的多孔分子筛催化剂及其制备方法。 催化剂由通过从包含具有Si-OH-Al-骨架的分子筛，水不溶性金属盐和磷酸盐化合物的原料混合物中蒸发水得到的产物组成。 即使在高温和高湿的气氛下，催化剂仍保持其物理和化学稳定性。 因此，即使在非均相催化反应如催化裂化反应，异构化反应，烷基化反应，酯化反应等各种氧化/还原反应中，在恶劣的高温高湿环境下使用，催化剂也具有优异的催化活性。

公开(公告)号：US20070052631A1

公开(公告)日：2007-03-08

申请号：US11481777

申请日：2006-07-05

Applicant: Chul Lee

Inventor： Chul Lee

IPC: G09G3/20

CPC classification number: G09G3/22 ,  G09G2320/029 ,  G09G2320/043 ,  G09G2320/0626 ,  G09G2330/02

Abstract: Disclosed are an electron emission display device and a driving method thereof capable of elevating a luminance and enhancing its lifetime. A pixel portion displays an image corresponding to voltages of a first electrode and a second electrode. A data driver transfers a data signal to the first electrode. A scan driver transfers a scan signal to the second electrode. A current measuring section measures an emission current flowing through the pixel portion. A power supply unit outputs an electric drive source. A voltage controller changes a voltage of an electric drive source corresponding to the emission current measured by the current measuring section. The voltage controller controls the emission current flowing through the pixel portion by the changed voltage of the electric drive source, so that a magnitude of the emission current is less than that of an initially set emission current.

Abstract translation: 公开了能够提高亮度并提高其寿命的电子发射显示装置及其驱动方法。 像素部显示与第一电极和第二电极的电压对应的图像。 数据驱动器将数据信号传送到第一电极。 扫描驱动器将扫描信号传送到第二电极。 电流测量部分测量流过像素部分的发射电流。 电源单元输出电驱动源。 电压控制器改变与由电流测量部测量的发射电流相对应的电驱动源的电压。 电压控制器通过电驱动源的改变的电压来控制流过像素部分的发射电流，使得发射电流的大小小于初始设定的发射电流的大小。

公开(公告)号：US20060267881A1

公开(公告)日：2006-11-30

申请号：US11408044

申请日：2006-04-21

Applicant: Dong Jeon ,  Chul Lee

Inventor： Dong Jeon ,  Chul Lee

IPC: G09G3/22

CPC classification number: G09G3/22 ,  G09G2310/0275 ,  G09G2320/0626 ,  G09G2360/16

Abstract: An electron emission display and a driving method thereof, where a brightness is adjusted differently according to a brightness of a frame in order to reduce power consumption and prevent a brazing fire from occurring, and to easily recognize a change of the brightness. The display includes a pixel portion adapted to receive a data signal and a scan signal, the pixel portion being further adapted to display an image, a data driver adapted to generate the data signal using video data, the data driver being further adapted to transfer the data signal to the pixel portion, a scan driver adapted to transfer the scan signal to the pixel portion, a timing controller adapted to transfer a drive signal to the data driver and to the scan driver, the drive signal driving the data driver and the scan driver, a data processor adapted to generate a control signal corresponding to frame data obtained by summing a size of video data input during one frame and a power supply section adapted to generate a drive power source and transfer the drive power source to the pixel portion, the data driver, the scan driver, the timing controller, and the data processor, wherein a brightness of the pixel portion is varied according to the control signal, and an amount varied of the brightness is determined based upon the size of the video data during the one frame.

Abstract translation: 一种电子发射显示器及其驱动方法，其中，为了降低功耗并防止发生钎焊火，可以根据框架的亮度对亮度进行不同的调整，并且容易地识别亮度的变化。 所述显示器包括适于接收数据信号和扫描信号的像素部分，所述像素部分还适于显示图像，适于使用视频数据生成数据信号的数据驱动器，所述数据驱动器还适于传送 数据信号发送到像素部分，适用于将扫描信号传送到像素部分的扫描驱动器，适于将驱动信号传送到数据驱动器和扫描驱动器的定时控制器，驱动数据驱动器的驱动信号和扫描 驱动器，数据处理器，适于生成对应于通过对在一帧期间输入的视频数据的大小进行求和获得的帧数据的控制信号，以及适于生成驱动电源并将驱动电源传送到像素部分的电源部， 数据驱动器，扫描驱动器，定时控制器和数据处理器，其中像素部分的亮度根据控制信号而变化，并且改变量 基于一帧期间的视频数据的大小来确定亮度。

公开(公告)号：US20060215472A1

公开(公告)日：2006-09-28

申请号：US11300009

申请日：2005-12-13

Applicant: Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Yeong-Taek Lee ,  Chul Lee

Inventor： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Yeong-Taek Lee ,  Chul Lee

IPC: G11C7/02

CPC classification number: G11C11/4097 ,  G11C2207/005

Abstract: Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.

Abstract translation: 提供了具有共享开放位线读出放大器架构的存储器件。 存储器件包括存储器单元阵列，每个存储单元阵列包括位线，以及读出放大器，配置为将至少两个位线耦合到存储单元阵列并被配置为耦合到不同存储单元阵列的至少两个位线。

公开(公告)号：US20060170852A1

公开(公告)日：2006-08-03

申请号：US11135990

申请日：2005-05-24

Applicant: Chul Lee ,  Kyung Lee

Inventor： Chul Lee ,  Kyung Lee

IPC: G02F1/1337

CPC classification number: G02F1/133711 ,  G02F1/134363

Abstract: Disclosed is an LCD with improved image retention for increased reliability and screen quality. The LCD includes lower and upper substrates provided with predetermined patterns, respectively, and positioned to face each other with a predetermined distance; a liquid crystal layer interposed between the lower and upper substrates; and alignment layers positioned between the lower substrate and the liquid crystal layer and the upper substrate and the liquid crystal layer, respectively, to determine the initial arrangement of liquid crystals. The alignment layers have bubbles formed therein to reduce the capacitance generated by the alignment layers and the difference in level of the lower substrate for improved image retention.

Abstract translation: 公开了具有改善的图像保持性以提高可靠性和屏幕质量的LCD。 LCD包括分别具有预定图案的下基板和上基板，并且以预定距离相对定位; 介于下基板和上基板之间的液晶层; 以及分别位于下基板和液晶层以及上基板和液晶层之间的取向层，以确定液晶的初始布置。 取向层具有形成在其中的气泡，以减小由取向层产生的电容和下基板的电平差，以改善图像保持。