公开(公告)号：DE112018002951T5

公开(公告)日：2020-04-02

申请号：DE112018002951

申请日：2018-07-19

Applicant: IBM

Inventor： GUPTA LOKESH ,  ANDERSON KYLER ,  ASH KEVIN JOHN ,  KALOS MATTHEW JOSEPH ,  PETERSON BETH ANN

IPC: G06F12/08

Abstract: Bereitgestellt werden ein Computerprogrammprodukt, ein System und ein Verfahren zum Verwenden eines Spurformatcodes in einem Cache-Steuerblock für eine Spur in einem Cache, um Lese- und Schreibanforderungen in Bezug auf die Spur im Cache zu verarbeiten. Eine Spurformattabelle ordnet Spurformatcodes zu Spurformatmetadaten zu. Es wird eine Ermittlung vorgenommen, ob die Spurformattabelle Spurformatmetadaten aufweist, die mit Spurformatmetadaten einer in den Cache verlagerten Spur übereinstimmen. Es wird eine Ermittlung vorgenommen, ob ein Spurformatcode aus der Spurformattabelle für die Spurformatmetadaten in der Spurformattabelle mit Spurformatmetadaten der verlagerten Spur übereinstimmt. Für die Spur, die zum Cache hinzugefügt wird, wird ein Cache-Steuerblock erzeugt, der den ermittelten Spurformatcode beinhaltet, wenn die Spurformattabelle die übereinstimmenden Spurformatmetadaten aufweist.

公开(公告)号：IN4679CHN2014A

公开(公告)日：2015-09-18

申请号：IN4679CHN2014

申请日：2014-06-20

Applicant: IBM

Inventor： GUPTA LOKESH MOHAN ,  KALOS MATTHEW JOSEPH ,  BENHASE MICHAEL THOMAS ,  NIELSEN KARL ALLEN ,  ASH KEVIN JOHN

IPC: G06F12/08

Abstract: Provided are a computer program product system and method for managing data in a cache system comprising a first cache a second cache and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted.

公开(公告)号：GB2522742A

公开(公告)日：2015-08-05

申请号：GB201419680

申请日：2014-11-05

Applicant: IBM

Inventor： ASH KEVIN JOHN ,  GUPTA LOKESH MOHAN

IPC: G06F3/06 ,  G06F12/08

Abstract: Embodiments for efficient thresholding of nonvolatile storage (NVS) for a plurality of types of storage rank groups by a processor. Target storage devices are determined in a pool of target storage devices as one of a hard disk drive (HDD) and a solid-state drive (SSD) device. Each target storage device classified into an SSD rank group, a Nearline rank group, an Enterprise rank group, and an Ultra-SSD rank group in the pool of target storage devices. The Nearline rank group and the Enterprise rank group comprise a HDD rank group, and the Nearline rank group, the Enterprise rank group, and the SSD rank group comprise the Non­Ultra-SSD rank group. Thresholds are adjusted for preventing space allocation in the NVS for at least one of the classified target storage devices based on one of the presence and absence of identified types of the classified target storage devices.

公开(公告)号：HK35392A

公开(公告)日：1992-05-29

申请号：HK35392

申请日：1992-05-21

Applicant: IBM

Inventor： ASH KEVIN JOHN ,  DERENBURGER JACK HARVEY ,  PARSONS RAYMOND LONNIE

IPC: G06F11/00 ,  G06F11/10 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/18 ,  G11C29/42 ,  G06F11/22

Abstract: A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.

公开(公告)号：GB2201016B

公开(公告)日：1991-03-13

申请号：GB8719405

申请日：1987-08-17

Applicant: IBM

Inventor： ASH KEVIN JOHN ,  DERENBURGER JACK HARVEY ,  PARSONS RAYMOND LONNIE

IPC: G06F11/00 ,  G06F11/10 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/18 ,  G11C29/42

Abstract: A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.

公开(公告)号：AU597140B2

公开(公告)日：1990-05-24

申请号：AU1035688

申请日：1988-01-18

Applicant: IBM

Inventor： ASH KEVIN JOHN ,  DERENBURGER JACK HARVEY ,  PARSONS RAYMOND LONNIE

IPC: G01R31/28 ,  G06F11/00 ,  G06F11/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/18 ,  G11C29/42

Abstract: A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.

公开(公告)号：GB2201016A

公开(公告)日：1988-08-17

申请号：GB8719405

申请日：1987-08-17

Applicant: IBM

Inventor： ASH KEVIN JOHN ,  DERENBURGER JACK HARVEY ,  PARSONS RAYMOND LONNIE

IPC: G06F11/00 ,  G06F11/10 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/18 ,  G11C29/42 ,  G06F11/22

Abstract: A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage word. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accessed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.