公开(公告)号：JP2010128960A

公开(公告)日：2010-06-10

申请号：JP2008305074

申请日：2008-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KAWAHITO MOTOHIRO

IPC: G06F9/45 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for comprehensively and automatically generating a prefetch instruction when a cache state includes three states: "having no data; for loading; and for both loading and storage", and to provide a compiler.
SOLUTION: The method for generating the prefetch instruction of the compiler includes: a step of specifying as an optimization target a loading instruction for causing a cache to transition from a state having no data to a state suitable for loading among instructions included in an area to be optimized and a storage instruction for causing the cache to transition from a state suitable for loading to a state suitable for loading and storage among the instructions included in the area to be optimized, for each of one or more areas to be optimized constituting a source program being a compile target; and a step of determining a position for inserting a prefetch instruction in the area to be optimized on the basis of the specified optimization target and a branch probability of each if sentence included in the source program, and generating the prefetch instruction at the position.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种当高速缓存状态包括三个状态时全面自动地生成预取指令的方法：“没有数据;用于加载;以及用于加载和存储”，并且提供编译器。 解决方案：用于生成编译器的预取指令的方法包括：将优先目标指定为使高速缓存从不具有数据的状态转换到适于在包含在其中的指令之间加载的状态的加载指令的步骤 要优化的区域和用于使缓存从适于加载的状态转换到适于加载和存储的状态的存储指令，用于要优化的一个或多个要优化的区域中的每个要优化的区域中的指令 构成作为编译目标的源程序; 以及根据指定的优化目标确定要在要优化的区域中插入预取指令的位置的步骤，以及在源程序中包括的每个if语句的分支概率，以及在该位置生成预取指令的步骤。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009110299A

公开(公告)日：2009-05-21

申请号：JP2007282322

申请日：2007-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KAWAHITO MOTOHIRO ,  MORIYAMA TAKAO ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/4435

Abstract: PROBLEM TO BE SOLVED: To optimize a process calculating a value to be assigned to a variable. SOLUTION: A compiler apparatus for optimizing a program includes: a range analysis unit for analyzing a range of a value assignable to the variable by the instruction, as a range of the variable in the case where the instruction is executed in terms of an instruction to assign a value to a variable in the program; a determination unit for determining if the execution result of the program does not change even if the instruction assigns any value in the range of the variable on the basis of the analyzed range of the variable; and a replacement unit for replacing the instruction to assign the value to the variable with an instruction to assign a constant value in the range of the variable to the variable on condition that the determination by the determination unit is formed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：优化计算要分配给变量的值的过程。 解决方案：用于优化程序的编译装置包括：范围分析单元，用于通过指令分析可分配给该变量的值的范围，作为在执行指令的情况下的变量的范围 为程序中的变量分配值的指令; 确定单元，用于确定程序的执行结果是否不改变，即使该指令基于变量的分析范围分配变量范围中的任何值; 以及替换单元，用于在形成由确定单元的确定的条件下，用用于将变量的范围中的常数值分配给变量的指令来替换指定值以赋值给变量的指令。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004021428A

公开(公告)日：2004-01-22

申请号：JP2002173212

申请日：2002-06-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KAWAHITO MOTOHIRO ,  KOSEKI SATOSHI

IPC: G06F9/45 ,  G05B19/42 ,  G06F9/44

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F9/45508

Abstract: PROBLEM TO BE SOLVED: To improve the executing efficiency of a program by reducing the influences of an explicit order for matching the images of local variables between a code train executed via an interpreter and a compiled code train for optimizing operation.
SOLUTION: This program conversion method comprises a first step of setting a code negligible in the certain deformation of the second code train out of codes in the first code train giving influences to the deformation of the second code train during transition from the first code train where an object to be executed by a program is executed via the interpreter to the second compiled code train and a second step of performing the certain deformation of the second code train while neglecting the set negligible code. It is acceptable that it includes a third step of generating a compensation code required for the deformation of the second code train including the propagation of a copying order and inserting it into the first code train.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002259135A

公开(公告)日：2002-09-13

申请号：JP2001055996

申请日：2001-02-28

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI ,  JOHN FARLEY

IPC: G06F9/45 ,  G06F9/44

Abstract: PROBLEM TO BE SOLVED: To shorten time required for compilation including optimization based on specification and to suppress memory consumption for compilation. SOLUTION: The compiler 10 is provided with an influence degree analysis part 12 for analyzing how much the execution speed of a program to be compiled can be improved by fixing the parameter of a prescribed instruction in the program to a specific state, a specification data selection part 13 for taking the statistics of appearance frequency in each state of the parameter of the instruction analyzed by the analysis part 12 and determining which state is to be adopted for the parameter of the instruction based on the obtained static information and a specified compiling processing part 14 for generating a specified pass fixing the parameter of the prescribed instruction to the specific state in the program based on the processing results of the analysis part 12 and the selection part 13.

公开(公告)号：JP2000207221A

公开(公告)日：2000-07-28

申请号：JP71299

申请日：1999-01-05

Applicant: IBM

Inventor： KAWAHITO MOTOHIRO ,  KOMATSU HIDEAKI ,  YASUE TOSHIAKI

IPC: G06F9/45 ,  G06F9/44

Abstract: PROBLEM TO BE SOLVED: To decrease the frequency of an array range check and to increase execution speed by generating a code for an array range check included in array range checks. SOLUTION: Array range checks, corresponding to array access operations, are integrated under specific conditions and the result is stored in a storage device (110). An array range check is assigned to one ore more flags (120). Codes to be stored in the assigned flags are generated and stored in a storage device (130). If versioning is carried out (140), a versioning header is generated by using the flags, and a version of flag check success and a version of flag check failure are generated and stored in the storage device (150). A code, which invalidates a code is generated and stored in the storage device (160). Consequently, array range checks which are to be removed becomes few.