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    22.
    发明专利
    未知

    公开(公告)号：DE3678123D1

    公开(公告)日：1991-04-18

    申请号：DE3678123

    申请日：1986-11-11

    Applicant: IBM

    Inventor： LOGUE JOSEPH C

    IPC: H01L21/822 ,  H01L21/66 ,  H01L21/82 ,  H01L25/065 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10 ,  H01L21/72 ,  H01L23/34

    Abstract: Balancing the values of physical parameters such as temperature between used and unused circuit islands (0000-0111), in a fault bypass wafer circuit module (11, or 11+12), is done by mandating circuit exercise within each island considered critical. Within individual critical exercise islands, thermostats (15) control heaters, or other physical parameter reporting means control transducers, to return the physical parameter to nominal values. Heavily exercised operational islands and unexercised faulty or good redundant islands could develop destructive thermal gradients and resulting operational or connection failures. To eliminate such physical gradients, circuit exercise is mandated in all circuit islands which receive no ordinary circuit exercise, simply to maintain physical balance. Temperature is the physical parameter of primary concern, but physical parameters include piezoelectric effects, capacitance, inductance, magnetism, radiation effects and voltage, as well as other physical parameters which may be related or derivative. Each island of concern as a critical exercise island is equipped with physical parameter balancing means (15), comprising a physical parameter sensor and transducer controlled by the sensor to alter that physical parameter. The physical parameter may be measured, may be detected at a threshold, or may be calculated by inference from exercise event counts. The counts may be taken externally in a computer (8), or internally by configuring an event counter (9) within the electronics of the island. An interposer and a conductive liquid for combined electrical and heat distribution are options.

    MODULAR MACROPROCESSING SYSTEM COMPRISING A MICROPROCESSOR AND AN EXTENDABLE NUMBER OF PROGRAMMED LOGIC ARRAYS
    25.
    发明专利
    MODULAR MACROPROCESSING SYSTEM COMPRISING A MICROPROCESSOR AND AN EXTENDABLE NUMBER OF PROGRAMMED LOGIC ARRAYS 未知

    公开(公告)号：CA1136768A

    公开(公告)日：1982-11-30

    申请号：CA341842

    申请日：1979-12-13

    Applicant: IBM

    Inventor： LOGUE JOSEPH C ,  WU WEI-WHA

    IPC: G06F7/00 ,  G06F9/22 ,  G06F9/30 ,  G06F13/12 ,  G06F15/78

    Abstract: MODULAR MACROPROCESSING SYSTEM COMPRISING A MICROPROCESSOR AND AN EXTENDABLE NUMBER OF PROGRAMMED LOGIC ARRAYS A modular system comprising a microprocessor having a system bus (control aaddress and data) and one or more programmed logic arrays connected to the system bus Three system configurations are shown by way of example, Macroprocessor, Peripheral Input/Output and Direct Memory Access applications. The microprocessor executes a standard set of instructions and addresses each programmed logic array. Each array executes a specific instruction, beyond the standard set of instructions, upon receipt of its address. FI 9-78-053

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