公开(公告)号：US3154744A

公开(公告)日：1964-10-27

申请号：US85852459

申请日：1959-12-09

Applicant: IBM

Inventor： MALEY GERALD A

IPC: H03K3/037 ,  H03K21/00

CPC classification number: H03K21/00 ,  H03K3/037

公开(公告)号：US3074640A

公开(公告)日：1963-01-22

申请号：US7662260

申请日：1960-12-19

Applicant: IBM

Inventor： MALEY GERALD A

IPC: G06F7/50 ,  G06F7/502 ,  H03K19/21

CPC classification number: G06F7/502 ,  H03K19/212

公开(公告)号：US3015043A

公开(公告)日：1961-12-26

申请号：US86267859

申请日：1959-12-29

Applicant: IBM

Inventor： MALEY GERALD A

IPC: H03K3/038 ,  H03K19/082

CPC classification number: H03K3/038 ,  H03K19/0823

公开(公告)号：US3015040A

公开(公告)日：1961-12-26

申请号：US1219960

申请日：1960-03-01

Applicant: IBM

Inventor： MALEY GERALD A ,  BOYLE WILLIAM W

IPC: H03K3/037

CPC classification number: H03K3/037

公开(公告)号：CA720964A

公开(公告)日：1965-11-02

申请号：CA720964D

Applicant: IBM

Inventor： LOW PAUL R ,  MALEY GERALD A ,  DOMENICO ROBERT J

公开(公告)号：CA653312A

公开(公告)日：1962-12-04

申请号：CA653312D

Applicant: IBM

Inventor： MALEY GERALD A

公开(公告)号：CA996261A

公开(公告)日：1976-08-31

申请号：CA166916

申请日：1973-03-13

Applicant: IBM

Inventor： HO IRVING T ,  MALEY GERALD A ,  YU HWA N

IPC: G11C17/00 ,  G11C7/20 ,  G11C11/35 ,  G11C11/404 ,  G11C17/12 ,  H01L27/108

Abstract: A latent image memory is selectively operable as either a read-write memory or a read-only memory. The memory comprises an array of cells each preferably consisting of a single active device. A first set of the cells are each adapted to store either one of two binary digits. A second set of the cells are each responsive to a first condition for storing either one of two binary digits and responsive to a second condition for storing only a single predetermined binary digit. Means are provided for selecting either the first condition to render the array operable as a read-write memory, or the second condition to render the array operable as a read-only memory. Each of the cells of the first set preferably comprises a field-effect transistor connected to a capacitor, and each of the cells of the second set preferably comprises a charge-coupled device.

公开(公告)号：CA699818A

公开(公告)日：1964-12-15

申请号：CA699818D

Applicant: IBM

Inventor： STAHL WILLIAM L ,  MALEY GERALD A

公开(公告)号：CA994916A

公开(公告)日：1976-08-10

申请号：CA172498

申请日：1973-05-28

Applicant: IBM

Inventor： MALEY GERALD A ,  RISEMAN JACOB

IPC: G06F9/50 ,  G06F11/34

公开(公告)号：CA974652A

公开(公告)日：1975-09-16

申请号：CA144163

申请日：1972-06-08

Applicant: IBM

Inventor： MALEY GERALD A

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/48

Abstract: A memory correcting system in accordance with this disclosure is an integral part of a digital electronic computer having a monolithic memory. The memory correcting system detects, records and analyzes errors occurring during normal operation of the computer. Also, the memory correcting system systematically addresses the monolithic memory on a cycle stealing basis monitoring the general health of the monolithic memory. The systematic reading and writing of all monolithic memory locations prevents the accumulating effects of random errors. By detecting single errors as rapidly as possible, the probability of acquiring additional errors that are above the correcting capabilities of the redundancy code are avoided.