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公开(公告)号：DE69030073T2
公开(公告)日：1997-09-18
申请号：DE69030073
申请日：1990-12-17
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI , SO BUM SUCK , RUTLEDGE ROBERT ANTHONY
Abstract: A method is disclosed for processing, in a signal processing channel, digital values corresponding to a digitized incoming analog signal representative of coded binary data. A state-dependent sequence detection algorithm includes two groups of appropriate functional expressions of digital sample values, which expressions are identical but offset one sample position from each other. During each iterating step with successive pairs of clock cycles, the value of each expression in the said two groups of expressions is precomputed from a preselected number of sample values ahead of a then current sample value; preselected ones of these expression values are compared against an appropriate threshold, which is the same for corresponding expressions of each group, to provide respective binary decision outputs corresponding to each of the two groups; and the current state value then advances to two next successive state values. During precomputation, a preselected greater number of sample values ahead of the current sample is preferably used in a pipelined configuration to allow additional time for precomputing said groups of expressions.
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公开(公告)号：SG147594G
公开(公告)日：1995-03-17
申请号：SG147594
申请日：1994-10-13
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: The present invention relates to an error correcting system for correcting errors in coded data recorded on a record medium in blocks of data bytes, in which each block comprises at least one sub-block, of data bytes and at least one sub-block error check byte (C1 to C3) and at least one block error check byte. The system is of the type which comprises error syndrome byte generating means, responsive to the error check bytes recorded in each sub-block, for generating, during read out of the data bytes and error check bytes in each sub-block, error syndrome bytes, and error correcting means, responsive to the error syndrome bytes, for correcting errors in the data bytes read out from each of the sub-blocks. … A system according to the invention is characterised in that it comprises… first error syndrome byte generating means for generating sub-block error syndrome bytes, corresponding to the check bytes associated with each sub-block,… first error syndrome processing circuitry (73), responsive to the sub-block error syndrome bytes, to detect and correct a predetermined number of errors in the data bytes in each sub-block and to detect but not correct another predetermined number of errors in the data bytes in each sub-block,… additional block error check byte generating means (72B) for generating additional block error check bytes (C0) for each block, corresponding to uncorrected errors in any sub-block in each block,… second error syndrome byte generating means for generating additional block error syndrome bytes, corresponding to the error check bytes in each block and the additional block error check bytes, and… second error syndrome processing circuitry (74 - 78), responsive to the block error syndrome bytes, to correct additional errors in the data bytes in each block.
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公开(公告)号：DE3852474D1
公开(公告)日：1995-01-26
申请号：DE3852474
申请日：1988-09-23
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A method and apparatus is disclosed for correcting up to two byte errors in encoded uncorrected data in records of a predetermined length. As illustrated, the records are subblocks of a block in a multi-level error correction code format. The data is read from a storage device and corrected by decoding and processing four syndromes of error (S1, S2, S3, S0) that are generated by means disclosed in the prior art. These syndromes are decoded in response to uncorrected errors in any one record by computing vectors (P, Q, and R), which are functions of the four syndromes. Binary numbers (u and v) are then determined from these vectors by table look-up to enable calculation of one value (d) from the sum of the binary numbers for determining error locations. Another value (t), mathematically related to the one value, is then determined by table look-up and the error location values (y and z) are determined by calculating the offset of binary numbers (u,v) from the other value (t). Finally, error patterns (Ey and Ez) are determined by table look-up.
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公开(公告)号：DE3888418D1
公开(公告)日：1994-04-21
申请号：DE3888418
申请日：1988-05-20
Applicant: IBM
Inventor： MARCUS BRIAN HARRY , PATEL ARVIND MOTIBHAI , SIEGEL PAUL HOWARD
IPC: H03M7/14 , H03M5/14 , H03M13/23 , H04L25/497
Abstract: There is disclosed a rate 8/9, constrained partial response class IV code having run length limitation parameters (0,3/5) is provided for any partial response (PR) signalling system employing maximum likelihood (ML) detection.
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公开(公告)号：DE3779553T2
公开(公告)日：1993-01-28
申请号：DE3779553
申请日：1987-09-08
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI , WANG DAVID TAR-WEI , YU WELLINGTON CHIA-PEIR
Abstract: In a data processing system in which two-level error correction is performed on variable length data being transferred between the host processor and the data storage device, the logical length of the data being transferred is computed during a fixed time gap with computation continuing after termination of the fixed time gap and commencement of the data transfer. The computation required for the logical length of the data field to accommodate two-level ECC is accomplished by first comparing the actual field length with a value predetermined by the subblock length of the two-level ECC. If the actual length is greater than the predetermined value, then a value equal to the subblock length plus first level ECC bytes is loaded into a counter which begins decrementing at the termination of the fixed time gap so as to synchronise the byte-by-byte transfer of the data. As the data is being transferred the computation continues. When the computation has been completed, a value equal to the difference between the computed logical length and the subblock length plus first level ECC bytes is loaded into other counters which begin decrementing when the first counter reaches zero. In this manner transfer of the data is not interrupted. This permits two-level ECC to be incorporated into prior data processing systems which utilise a conventional track format with predetermined fixed time gaps, even though such fixed time gaps would otherwise be of insufficient duration to permit computation of the logical length required for two-level ECC.
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Patent Agency Ranking
公开(公告)号：ZA8308482B
公开(公告)日：1984-10-31
申请号：ZA8308482
申请日：1983-11-14
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
CPC classification number: G11B20/1809 , H03M13/15
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公开(公告)号：BR8400758A
公开(公告)日：1984-10-02
申请号：BR8400758
申请日：1984-02-20
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).
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公开(公告)号：AU2467084A
公开(公告)日：1984-09-06
申请号：AU2467084
申请日：1984-02-16
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).
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公开(公告)号：BR8307182A
公开(公告)日：1984-08-07
申请号：BR8307182
申请日：1983-12-27
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
IPC: G06F11/10 , G06F20060101 , G06F11/08 , G06K20060101 , G11B5/09 , H03M13/00 , H03M13/15
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公开(公告)号：DK108384D0
公开(公告)日：1984-02-27
申请号：DK108384
申请日：1984-02-27
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).
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