公开(公告)号：DE3064712D1

公开(公告)日：1983-10-06

申请号：DE3064712

申请日：1980-10-23

Applicant: IBM

Inventor： SCHLIG EUGENE STEWART

IPC: G11C8/16 ,  G11C11/411 ,  G11C8/00 ,  G11C11/40

Abstract: A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal. The emitters of the cross-connected flip-flop transistors are connected to an associated mode select line over which is applied a signal having a potential defining a write mode condition and a signal having a lower potential defining a read mode condition for the cell. Each pair of bit/sense lines and associated pair of accessing transistors that is added to each of the cells of a memory array may be operated to add an additional concurrent write of one word and a read of a different word for the array.

公开(公告)号：DE2753492A1

公开(公告)日：1978-07-06

申请号：DE2753492

申请日：1977-12-01

Applicant: IBM

Inventor： SCHLIG EUGENE STEWART ,  STILWELL JUN GEORGE RAYMOND

IPC: G09G3/28 ,  G09G3/288 ,  G09F9/30 ,  H01J61/92

公开(公告)号：DE2734202A1

公开(公告)日：1978-02-23

申请号：DE2734202

申请日：1977-07-29

Applicant: IBM

Inventor： SCHLIG EUGENE STEWART ,  STILWELL JUN GEORGE RAYMOND

IPC: H04N5/66 ,  G06F3/033 ,  G06F3/038 ,  G06F3/041 ,  G06F3/048 ,  G09G3/20 ,  G09G3/28 ,  G09F9/30 ,  H01J61/92

Abstract: LIGHT PEN DETECTION AND TRACKING WITH AC PLASMA DISPLAY PANEL A light pen detection and tracking scheme for detecting and tracking both "on" and "off" cells with a single cursor voltage waveform in an AC gas discharge display panel. The special cursor voltage waveform is applied to the panel during the sustain cycle, in either a line-by-line or binary scanning fashion, to momentarily fire both "on" and "off" cells so that they may be detected by the light pen without a loss of the memory state of the cells. A cross-hair cursor is automatically displayed at the pen position when the search scan is complete. Since both "on" and "off" cells are detected, the system can respond to pen motion by repeating the search to reacquire the pen, so that no special tracking strategy is needed.

公开(公告)号：DE2734543A1

公开(公告)日：1978-02-16

申请号：DE2734543

申请日：1977-07-30

Applicant: IBM

Inventor： SCHLIG EUGENE STEWART ,  STILWELL JUN GEORGE RAYMOND

IPC: G06F3/023 ,  G06F3/048 ,  G09G3/20 ,  G09G3/28 ,  G09G3/288 ,  G09G5/08 ,  G11C11/28 ,  G09F9/30 ,  H01J61/92

Abstract: A nondestructive, transparent cursor for AC plasma displays may be superimposed electronically over a displayed image without regenerating the original image each time the cursor is moved. The cursor is displayed by means of a special cursor drive waveform which discharges both previously "on" and "off" cells which form the cursor but permits reversion of the cells to their original state when the cursor drive waveform is removed and the normal sustaining waveform is restored.

公开(公告)号：DE1263112B

公开(公告)日：1968-03-14

申请号：DEJ0022820

申请日：1962-12-12

Applicant: IBM

Inventor： SCHLIG EUGENE STEWART ,  SOBOL HAROLD

IPC: H03B15/00

公开(公告)号：GB973437A

公开(公告)日：1964-10-28

申请号：GB2901961

申请日：1961-08-11

Applicant: IBM

Inventor： SCHLIG EUGENE STEWART ,  LENTZ JOHN JACOB

IPC: G11C11/44 ,  H03F19/00

Abstract: 973,437. Superconductive amplifiers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 11, 1961, No. 29019/61. Heading H3B. In a superconductive amplifier, gate conductors 20, 21, Fig. 3, are fed in parallel by a source 24 of constant current 2I 1 where I 1 is a little less than the critical current Ic necessary to drive a gate conductor resistive. Current in series connected control conductors 22, 23 tends to aid and to oppose respectively the magnetic effects of the gate conductors 20, 21. If control current flows from terminal 27 to terminal 28, gate 20 goes resistive and current is shifted from gate 20 to gate 21 until both gates are again superconducting but carry unequal currents. The current shifted is a measure of the control signal. In Fig. 5, a high inductance 34 and a low resistance 3 are connected in parallel with the gate conductors 20, 23. The current supply is adjusted to be slightly greater than the sum of the critical current for the two gate conductors. Automatically, low resistance branch 34, 35 takes current sufficient to reduce the current in conductors 20, 21 until at least one conductor becomes superconductive. In Fig. 6, series connected control conductors 57, 58, 59 and 60, 61, 62 control the shift of current between parallel connected gate conductors 43, 44, 45 and 60, 61, 62. Element construction.-A gate conductor 10, Fig. 1, comprises a thin film mounted on a planar backing 12. A thin film control conductor 11 narrower than the gate conductor is mounted on the gate conductor with an intervening layer of insulating material.