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    22.
    发明专利
    未知

    公开(公告)号：MX168088B

    公开(公告)日：1993-05-03

    申请号：MX1744889

    申请日：1989-09-06

    Applicant: IBM

    Inventor： SHERMAN ARTHUR MICHAEL ,  YANKER PETER CORNELIUS

    IPC: G06F12/04 ,  G09G5/14 ,  G06F12/00 ,  G09G5/36 ,  G09G5/39

    Abstract: Display data units are transferred in a graphic display PC/interface system which includes three memory units: a source memory (10) which is addressed in planar byte increments and stores display data units on a bit per plane basis; a target memory (42) for storing display data units in a manner suitable for operation of a display unit; and a window buffer (37) for transferring display data units from the source memory to the target memory. A guantity of display data unit bytes are transferred from the source memory (10) to the target memory (42) by accessing pairs of planar bytes, which pair of planar bytes may have a display data unit byte bridging therebetween. The method comprises selecting a first pair of planar bytes from the source memory; aligning the display data unit byte which lies totally within the selected first pair of planar bytes; selecting a second pair of planar bytes from the source memory; aligning the display data unit byte which lies totally within the second selected pair of planar bytes; consolidating the display data unit byte which bridges between the first and second pairs of selected planar bytes; aligning the consolidated display data unit byte; and transferring aligned display data unit bytes to the window buffer means.

    SISTEMA Y METODO DE REVESTIMIENTO DE IMAGEN DIGITAL
    23.
    发明专利
    SISTEMA Y METODO DE REVESTIMIENTO DE IMAGEN DIGITAL 未知

    公开(公告)号：PE8491A1

    公开(公告)日：1991-03-18

    申请号：PE17057590

    申请日：1990-06-07

    Applicant: IBM

    Inventor： BAYLEY MICHAEL WILLIAM RONALD ,  YANKER PETER CORNELIUS

    IPC: G06T3/00 ,  G09G1/16 ,  G09G5/393

    Abstract: CARACTERIZADO PORQUE DICHO SISTEMA DE PROCESAMIENTO DE DATOS INCLUYE UNA MEMORIA FUENTE DE UNIDAD DE DATOS, ORIENTADA EN FORMA DE UN BIT PLANAR, UNA MEMORIA OBJETO QUE POSEE UNA PLURALIDAD DE PLANOS, CADA PLANO COMPRENDE UNA PLURALIDAD DE UNIDADES DE DATOS QUE INCLUYEN UNIDADES DE DATOS MULTIBIT DISPUESTOS EN SERIE, EL BUFFER PARA TRANSFERIR DATOS DE DICHA MEMORIA FUENTE A LA MEMORIA OBJETO REFERIDA Y LOS MEDIOS DE INHIBICION DE TRANSFERENCIA PARA EVITAR QUE CIERTAS UNIDADES DE DATOS, RECUBRA LAS UNIDADES DE DATOS QUE YA SE ENCUENTRAN EN LA MEMORIA OBJETO REFERIDA

    25.
    发明专利
    未知

    公开(公告)号：ES2080074T3

    公开(公告)日：1996-02-01

    申请号：ES89308308

    申请日：1989-08-16

    Applicant: IBM

    Inventor： SHERMAN ARTHUR MICHAEL ,  YANKER PETER CORNELIUS

    IPC: G06F12/04 ,  G09G5/14 ,  G09G5/36 ,  G06F12/00 ,  G09G5/39 ,  G06F12/02 ,  G06F3/14 ,  G06T1/60

    Abstract: Display data units are transferred in a graphic display PC/interface system which includes three memory units: a source memory (10) which is addressed in planar byte increments and stores display data units on a bit per plane basis; a target memory (42) for storing display data units in a manner suitable for operation of a display unit; and a window buffer (37) for transferring display data units from the source memory to the target memory. A guantity of display data unit bytes are transferred from the source memory (10) to the target memory (42) by accessing pairs of planar bytes, which pair of planar bytes may have a display data unit byte bridging therebetween. The method comprises selecting a first pair of planar bytes from the source memory; aligning the display data unit byte which lies totally within the selected first pair of planar bytes; selecting a second pair of planar bytes from the source memory; aligning the display data unit byte which lies totally within the second selected pair of planar bytes; consolidating the display data unit byte which bridges between the first and second pairs of selected planar bytes; aligning the consolidated display data unit byte; and transferring aligned display data unit bytes to the window buffer means.

    HIGH SPEED METHOD FOR DATA TRANSFER
    28.
    发明专利
    HIGH SPEED METHOD FOR DATA TRANSFER 未知

    公开(公告)号：AU609635B2

    公开(公告)日：1991-05-02

    申请号：AU3947189

    申请日：1989-08-10

    Applicant: IBM

    Inventor： YANKER PETER CORNELIUS ,  SHERMAN ARTHUR MICHAEL

    IPC: G06F12/00 ,  G06F12/04 ,  G06T1/60 ,  G09G5/36 ,  G09G5/39 ,  G06F13/00

    Abstract: The first step in a method for transferring data units from a serially organized memory (12) to a bit planar organized memory (14) comprises selecting a plurality of data units from the serially organized memory. A bit pattern from the selected data units is then captured, which bit pattern includes only bits to be stored in a subset of the storage planes of the bit planar organized memory. The bit pattern is processed to isolate from it, subsidiary bit patterns, one bit pattern for each storage plane in the bit planar memory. Each subsidiary bit pattern is then translated so that its bit sequence is properly oriented and is then stored in a plane of the bit planar organized memory. In a preferred embodiment of the invention, the translations take place as the result of a table look-up step.

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