公开(公告)号：JP2012156532A

公开(公告)日：2012-08-16

申请号：JP2012068168

申请日：2012-03-23

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： USUI TAKAMASA ,  WATABE TADAYOSHI ,  NASU HAYATO

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which a concentration of an impurity metal remained in wiring is low.SOLUTION: This manufacturing method includes the steps of: forming an insulation film on a semiconductor substrate; forming a recess part in the insulation film; forming a precursor film containing a predetermined metal element on the surface of the insulation film having the recess part formed therein; depositing a wiring forming film on the precursor film; heating the deposited article in an oxidizing atmosphere, thereby making the precursor film react with the insulation film, and forming a self-forming barrier film containing a compound as a main component, which includes a predetermined metal element and a constituent element of the insulation film on the boundary surface of the precursor film and the insulation film; diffusing and moving the unreacted predetermined metal elements in the wiring forming film, and making the elements react with oxygen in the atmosphere on the surface of the wiring forming film, and making the reacted elements precipitated as an unreacted metal oxide film; removing the unreacted metal oxide film; depositing the same material as the wiring forming film on the wiring forming film after the step of removing the unreacted metal oxide film, and additionally depositing the wiring forming film; and subsequently flattening the wiring forming film until the insulation film outside the recess part is exposed, to form a wiring structure.

Abstract translation: 要解决的问题：提供一种其中在布线中残留杂质金属的浓度低的半导体器件的制造方法。 解决方案：该制造方法包括以下步骤：在半导体衬底上形成绝缘膜; 在所述绝缘膜中形成凹部; 在其中形成有凹部的绝缘膜的表面上形成含有预定金属元素的前体膜; 在前体膜上沉积布线形成膜; 在氧化气氛中加热沉积物，由此使前体膜与绝缘膜反应，并且形成含有化合物作为主要成分的自形成阻挡膜，该化合物包括预定的金属元素和绝缘膜的构成元素 在前体膜和绝缘膜的边界表面上; 扩散和移动布线形成膜中的未反应的预定金属元素，并使元素与布线形成膜的表面上的大气中的氧反应，并使反应的元素作为未反应的金属氧化物膜沉淀; 去除未反应的金属氧化物膜; 在去除未反应的金属氧化物膜的步骤之后，在布线形成膜上沉积与布线形成膜相同的材料，并且另外沉积布线形成膜; 然后使布线形成膜平坦化，直到凹部外的绝缘膜露出，形成布线结构。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2008153539A

公开(公告)日：2008-07-03

申请号：JP2006341761

申请日：2006-12-19

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI TAKAMASA ,  SHIBATA HIDEKI ,  MUROFUSHI TADASHI ,  JINBO MASAKAZU ,  HIRAYAMA HIROSHI

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04

CPC classification number: H01L23/5222 ,  H01L23/522 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To suppress deformation of an interlayer insulating film due to temperature rise in a hollow structure. SOLUTION: This semiconductor device includes first and second wiring layers L4, L5 each having a hollow structure and stacked vertically so as to be adjacent to each other on a semiconductor substrate S, a dummy pattern P formed in the first wiring structure L4 and not working as a signal line, and a conductive pattern P formed in the second wiring layer L5. Viewed from above the semiconductor substrate S, the dummy pattern P and the conductive pattern P each have a portion overlapping over each other and the other portion. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：抑制由于中空结构中的温度升高引起的层间绝缘膜的变形。 解决方案：该半导体器件包括第一和第二布线层L4，L5，每个布线层具有中空结构，并且在半导体基板S上彼此相邻地垂直堆叠，形成在第一布线结构L4中的虚设图案 并且不作为信号线工作，以及形成在第二布线层L5中的导电图案P. 从半导体基板S的上方观察，虚设图案P和导电图案P各自具有彼此重叠的部分和另一部分。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008060414A

公开(公告)日：2008-03-13

申请号：JP2006236809

申请日：2006-08-31

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： NASU ISATO ,  USUI TAKAMASA ,  TSUMURA KAZUMICHI ,  HAYASHI HIROMI

IPC: H01L21/3205 ,  H01L23/52

CPC classification number: H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device for improving the reliability by preventing a conductive member from being oxidized, and to provide a manufacturing method of the semiconductor device. SOLUTION: A first insulating layer 100 is formed on a semiconductor substrate; a groove 107 is formed on the first insulating layer 100; a wiring layer 101 containing copper on the surface is formed in the groove 107; the surface of the wiring layer 101 is activated to form a cap film 105, containing cobalt on the surface of the wiring layer 101 by subjecting it to electroless plating method; plasma treatment is performed on the surface of the wiring layer 101, excluding the forming section of the cap film 105 by reactive gas containing silicon and nitrogen; a copper silicide film 106 containing nitrogen is formed; and a second insulating layer 103 is formed on the first insulating layer 100, the cap film 105, and the copper silicide film 106 containing nitrogen. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过防止导电部件被氧化来提高可靠性的半导体器件，并提供半导体器件的制造方法。 解决方案：在半导体衬底上形成第一绝缘层100; 在第一绝缘层100上形成有沟槽107; 表面上含有铜的布线层101形成在槽107中; 通过对布线层101的表面进行化学镀处理，使布线层101的表面活化，形成含有钴的盖膜105， 除了含有硅和氮的反应性气体之外，在覆盖膜105的形成部分之外的布线层101的表面上进行等离子体处理; 形成含氮的硅化铜膜106; 并且在第一绝缘层100，盖膜105和含氮的硅化铜膜106上形成第二绝缘层103。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007335429A

公开(公告)日：2007-12-27

申请号：JP2006161864

申请日：2006-06-12

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： HAYASHI HIROMI ,  USUI TAKAMASA

IPC: H01L21/3205 ,  H01L23/12 ,  H01L23/52

CPC classification number: H01L24/05 ,  H01L2224/02166 ,  H01L2224/05554

Abstract: PROBLEM TO BE SOLVED: To suppress increase in k value of a low permeability insulating film or oxidation of interconnection in an element region, by preventing the low permeability insulating film from being damaged in a pad region, or preventing a moisture absorption state based on the damage from being transmitted to the low permeability insulating film or the interconnection in the element region. SOLUTION: The semiconductor device 10 comprises a semiconductor substrate 13 having a pad region 11 and an element region 12. On the semiconductor substrate 13, an interconnection layer 16 is provided having a low permeability insulating film 14 and a Cu interconnection 15. A moisture absorption prevention wall 19 separating the pad region 11 and the element region 12 is provided in the interconnection layer 16. The interconnection layer 16 is covered with a passivation film 18 excepting the exposure of an electrode pad 17. On the interconnection layer 16 in the pad region 11, the electrode pad 17 is provided as connected electrically with the Cu interconnection 15 in the element region 12 by a lead-out wire 20 insulated with the passivation film 18. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了抑制低导磁率绝缘膜的k值的增加或元件区域中的互连的氧化，通过防止低导磁率绝缘膜在焊盘区域中被损坏或防止吸湿状态 基于传递到低磁导率绝缘膜的损坏或元件区域中的互连。 解决方案：半导体器件10包括具有焊盘区域11和元件区域12的半导体衬底13.在半导体衬底13上，提供具有低导磁率绝缘膜14和Cu互连15的互连层16。 在互连层16中设置有分隔焊盘区域11和元件区域12的吸湿防止壁19.互连层16除了电极焊盘17的暴露之外被钝化膜18覆盖。在互连层16上 焊盘区域11，电极焊盘17被设置为通过与钝化膜18绝缘的引出线20与元件区域12中的Cu互连15电连接。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007306010A

公开(公告)日：2007-11-22

申请号：JP2007148693

申请日：2007-06-04

Applicant: Ibiden Co Ltd ,  Tokyo Electron Ltd ,  Toshiba Corp ,  イビデン株式会社 ,  東京エレクトロン株式会社 ,  株式会社東芝

Inventor： TAKEKOSHI KIYOSHI ,  HOSAKA HISATOMI ,  HAGIWARA JUNICHI ,  HATSUKA KUNIHIKO ,  USUI TAKAMASA ,  KANEKO HISAFUMI ,  HAYASAKA NOBUO ,  IDO YOSHIYUKI

IPC: H01L21/66

Abstract: PROBLEM TO BE SOLVED: To provide a shell by which the reliability of a semiconductor element is evaluated and tested quickly, efficiently, and highly reliably on a wafer level. SOLUTION: The shell has a thermal resistance substrate and a conductor circuit in which a connecting pad portion is formed on the thermal resistance substrate, and is used when evaluating and testing the reliability at a temperature of 160°C or more. The shell has a contactor 11 in which a coefficient of thermal expansion of the thermal resistance substrate is 1-50 ppm/°C, and a wafer holder 32. When testing the reliability, a wafer W is laid on the wafer holder 32, in the state where the connecting pad portion of the contactor 11 and an electrode pad of the wafer W are collectively brought into contact, the wafer holder 32, the wafer W and the contactor 11 are integrated. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种壳体，通过该壳体可以在晶片级上快速，有效且高可靠地评估和测试半导体元件的可靠性。 解决方案：壳体具有耐热基板和导体电路，其中在热电阻基板上形成连接焊盘部分，并且当在160℃或更高的温度下评估和测试可靠性时使用。 壳体具有接触器11，其中热电阻基板的热膨胀系数为1-50ppm /℃，晶片保持器32.当测试可靠性时，将晶片W放置在晶片保持器32上， 接触器11的连接焊盘部分和晶片W的电极焊盘共同接触的状态，晶片保持器32，晶片W和接触器11被集成。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007067069A

公开(公告)日：2007-03-15

申请号：JP2005249440

申请日：2005-08-30

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： USUI TAKAMASA ,  SHIBATA HIDEKI ,  MUROFUSHI TADASHI ,  JINBO MASAKAZU ,  HIRAYAMA HIROSHI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a reliable multilayer wiring structure using an interlayer insulating film with high void ratio. SOLUTION: The multilayer wiring structure comprises a lower wiring layer which has an interlayer film with 50% or more of void ratio, and an upper wiring layer with low void ratio. In the structure, the upper wiring layer with low void ratio having an interlayer film with much thickness is supported by stacked vias 70 which are formed via wiring layers so as to connect the wiring layers perpendicularly, and continuously to the substrate surface and by a perimeter ring 80 provided in a chip peripheral part. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用具有高空隙率的层间绝缘膜具有可靠的多层布线结构的半导体器件。 解决方案：多层布线结构包括具有50％以上空隙率的中间膜的下布线层和低空隙率的上布线层。 在该结构中，具有厚度较厚的中间膜的具有低空隙率的上布线层由堆叠的通孔70支撑，该通孔70经由布线层形成，以便将布线层垂直地连接到基板表面和周边 环80设置在芯片周边部分中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007012922A

公开(公告)日：2007-01-18

申请号：JP2005192652

申请日：2005-06-30

Applicant: Toshiba Corp ,  Toshiba Microelectronics Corp ,  東芝マイクロエレクトロニクス株式会社 ,  株式会社東芝

Inventor： NASU ISATO ,  SHIBATA HIDEKI ,  USUI TAKAMASA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/516 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7881

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device advantageous for scaling-down, and to provide its fabrication process.
SOLUTION: The semiconductor device comprises a gate insulating film 12 equipped at least with a first insulating film 21 provided in the major surface of a semiconductor device, and a first high dielectric film 22-1 principally comprising a compound of the constitutive element of the first insulating film and a predetermined metal element provided on the first insulating film and having a dielectric constant higher than that of the first insulating film, a gate electrode 13 of Cu or principally comprising Cu provided on the gate insulating film 12, and a source or a drain 15 provided in the semiconductor substrate while being isolated so that the gate electrode is inserted.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供有利于缩小的半导体器件，并提供其制造工艺。 解决方案：半导体器件包括至少配备有设置在半导体器件的主表面中的第一绝缘膜21的栅极绝缘膜12和主要包含本构元件的化合物的第一高介电膜22-1 的第一绝缘膜和设置在第一绝缘膜上并且具有比第一绝缘膜高的介电常数的预定金属元件，设置在栅极绝缘膜12上的Cu或主要包含Cu的栅极13，以及 源极或漏极15，其被隔离设置在半导体衬底中，使得栅电极被插入。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006202852A

公开(公告)日：2006-08-03

申请号：JP2005010732

申请日：2005-01-18

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KOBAYASHI TAKAYO ,  USUI TAKAMASA

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To suppress malfunction due to stress migration. SOLUTION: A lower layer wiring 16 is formed with a first barrier metal layer 14 and a wiring material 15 mainly composed of Cu embedded in a wiring groove formed in a first interlayer insulting film 13. Insulating films 17 and 18 are formed on the first interlayer insulating film 13 and a lower layer wiring 16. A second barrier metal layer 20 and a plug material 21 mainly composed of Cu are embedded in a hole formed in the insulating films 17 and 18, and a via plug 22a and a slit-like dummy plug 22b are formed. The slit-like dummy plug 22b is not connected to an upper layer wiring 26a. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：抑制由于应力迁移引起的故障。 解决方案：下层布线16形成有第一阻挡金属层14和主要由嵌入在形成在第一层间绝缘膜13中的布线槽中的Cu构成的布线材料15.绝缘膜17和18形成在 第一层间绝缘膜13和下层布线16.主要由Cu构成的第二阻挡金属层20和塞子材料21嵌入形成在绝缘膜17和18中的孔中，并且通孔塞22a和狭缝 形状的虚拟插头22b。 狭缝状的虚拟插头22b不与上层布线26a连接。 版权所有（C）2006，JPO＆NCIPI