公开(公告)号：US20180285109A1

公开(公告)日：2018-10-04

申请号：US15477012

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06T1/60 ,  G06F9/50 ,  G06F12/0802 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US20170091981A1

公开(公告)日：2017-03-30

申请号：US15335670

申请日：2016-10-27

Applicant: Intel Corporation

Inventor： Adam W. Herr ,  Adam T. Lake ,  Ryan T. Tabrah

IPC: G06T15/00 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T19/006

Abstract: Methods and systems may provide for an apparatus having a graphics processing unit (GPU) and a non-volatile memory dedicated to the GPU. If a request for content is detected, a determination may be made as to whether the non-volatile memory contains the content.

公开(公告)号：US11941169B2

公开(公告)日：2024-03-26

申请号：US17683533

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Brent E. Insko ,  Prasoonkumar Surti ,  Adam T. Lake ,  Peter L. Doyle ,  Daniel Pohl

IPC: G06F3/01 ,  G02B27/00

CPC classification number: G06F3/013 ,  G02B27/0093 ,  G06F3/011

Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

公开(公告)号：US11688122B2

公开(公告)日：2023-06-27

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

CPC classification number: G06T15/005 ,  G06F9/4881 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US20210263742A1

公开(公告)日：2021-08-26

申请号：US17195132

申请日：2021-03-08

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06F9/50 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US10942740B2

公开(公告)日：2021-03-09

申请号：US16794973

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  Abhishek R. Appu

IPC: G06F9/30 ,  G06F9/50 ,  G06T15/00 ,  G09G5/36 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.

公开(公告)号：US20210035270A1

公开(公告)日：2021-02-04

申请号：US16929787

申请日：2020-07-15

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06T5/00 ,  G06T15/50 ,  G06T15/00 ,  G06T1/20 ,  G06T9/00 ,  G06T11/40

Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US20200258284A1

公开(公告)日：2020-08-13

申请号：US16793504

申请日：2020-02-18

Applicant: Intel Corporation

Inventor： Adam W. Herr ,  Adam T. Lake ,  Ryan T. Tabrah

IPC: G06T15/00 ,  G06T1/60 ,  G06T19/00

Abstract: Methods and systems may provide for an apparatus having a graphics processing unit (GPU) and a non-volatile memory dedicated to the GPU. If a request for content is detected, a determination may be made as to whether the non-volatile memory contains the content.

公开(公告)号：US10565676B2

公开(公告)日：2020-02-18

申请号：US15488547

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC: G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US10475150B2

公开(公告)日：2019-11-12

申请号：US15721063

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： William A. Hux ,  Girish Ravunnikutty ,  Adam T. Lake

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/50 ,  G06F9/48

Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including a high priority command streamer to dispatch high priority commands from an application, a normal priority command streamer to receive normal priority commands through a command path, one or more execution units, and a thread dispatcher. The thread dispatcher to dispatch normal priority commands to the one or more executions units, determine the high priority command streamer includes at least one command, cause the one or more execution units to save their states, and dispatch at least one command from the high priority queue to the one or more execution units.