公开(公告)号：US10074718B2

公开(公告)日：2018-09-11

申请号：US15485004

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786 ,  B82Y10/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

公开(公告)号：US09847432B2

公开(公告)日：2017-12-19

申请号：US14912403

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz Gardner ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Robert Chau

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/786 ,  H01L29/778 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/41 ,  H01L29/20

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78681

Abstract: Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

公开(公告)号：US20170236704A1

公开(公告)日：2017-08-17

申请号：US15504634

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L21/8252 ,  H01L29/16 ,  H01L29/78 ,  H01L29/267 ,  H01L27/06 ,  H01L29/778

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7851

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

公开(公告)号：US20170213892A1

公开(公告)日：2017-07-27

申请号：US15481200

申请日：2017-04-06

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/205 ,  H01L21/324 ,  H01L21/02 ,  H01L21/308 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684

Abstract: A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation.

公开(公告)号：US20170207307A1

公开(公告)日：2017-07-20

申请号：US15464931

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sherry Taft ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/20 ,  H01L29/06 ,  H01L21/02 ,  H01L29/04 ,  H01L21/762

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

公开(公告)号：US20170194506A1

公开(公告)日：2017-07-06

申请号：US15465448

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

公开(公告)号：US20170194142A1

公开(公告)日：2017-07-06

申请号：US15464888

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US09698013B2

公开(公告)日：2017-07-04

申请号：US14908987

申请日：2013-09-04

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Niti Goel ,  Sanaz K. Gardner ,  Pragyansri Pathi ,  Matthew V. Metz ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  James M. Powers ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US09685508B2

公开(公告)日：2017-06-20

申请号：US14946718

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170154981A1

公开(公告)日：2017-06-01

申请号：US15430348

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.