公开(公告)号：US12108029B2

公开(公告)日：2024-10-01

申请号：US17133324

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Sri Ranjan Srikantam ,  Prasanna Kumar Mandapadi Ramasubramanian ,  Changliang Wang ,  Kseniya Tikhomirova ,  Sergey Solodkov

IPC: H04N19/105 ,  H04N19/146 ,  H04N19/159 ,  H04N19/172 ,  H04N19/30

CPC classification number: H04N19/105 ,  H04N19/146 ,  H04N19/159 ,  H04N19/172 ,  H04N19/30

Abstract: Techniques related to video coding include efficient frame loss recovery using a feedback channel acknowledgement to decode base layer frames.

公开(公告)号：US20240135485A1

公开(公告)日：2024-04-25

申请号：US18460044

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Fan He ,  Yi Qian ,  Ning Luo ,  Yunbiao Lin ,  Changliang Wang ,  Ximin Zhang

IPC: G06T1/20 ,  G06N3/092 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06N3/092 ,  G06T15/005

Abstract: The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration parameters associated with three-dimensional 3D rendering, pre-processing and video encoding of the graphics pipeline; and tune the graphics pipeline with the determined configuration parameters for processing a next frame.

公开(公告)号：US11861761B2

公开(公告)日：2024-01-02

申请号：US17095590

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04

CPC classification number: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US11763010B2

公开(公告)日：2023-09-19

申请号：US17589488

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： Ashwin Muppalla ,  Changliang Wang ,  Penne Lee

IPC: H04L29/06 ,  G06F21/60 ,  G06T1/20 ,  G06N3/04 ,  H04L9/08 ,  G06N3/08 ,  G06F16/23 ,  G06T7/00 ,  G09C5/00 ,  H04L9/06

CPC classification number: G06F21/602 ,  G06F16/2365 ,  G06N3/04 ,  G06N3/08 ,  G06T1/20 ,  G06T7/0002 ,  G09C5/00 ,  H04L9/0618 ,  H04L9/0819 ,  H04L2209/60

Abstract: Methods, articles, and systems of computer graphics processing system validation for processing of encrypted image content are disclosed herein.

公开(公告)号：US20230260075A1

公开(公告)日：2023-08-17

申请号：US18305904

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/0802 ,  G06N5/04 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a state of multiple intellectual property (IP) cores that have access to a common cache via a central fabric is observed. Responsive to the observed state being indicative of performance of a standalone workload by a first IP core of the multiple IP cores, the common cache is treated as a local cache of the first IP core by powering off the central fabric and causing the first IP core to access the common cache via a low power access path between the first IP core and the common cache that is outside of the central fabric.

公开(公告)号：US20220408097A1

公开(公告)日：2022-12-22

申请号：US17764162

申请日：2019-11-14

Applicant: Intel Corporation

Inventor： Yunbiao Lin ,  Changliang Wang ,  Ximin Zhang ,  Fan He ,  Jill Boyce ,  Sri Ranjan SRIKANTAM

IPC: H04N19/146 ,  H04N19/142 ,  H04N19/184 ,  H04N19/172

Abstract: An example apparatus for adaptively encoding video frames includes a network analyzer to predict an instant bitrate based on channel throughput feedback received from a network. The apparatus also includes a content analyzer to generate ladder info based on a received frame. The apparatus further includes an adaptive decision executer to determine a frame rate, a video resolution, and a target frame size based on the predicted instant bitrate and the ladder outputs. The apparatus further includes an encoder to encode the frame based on the frame rate, the video resolution, and the target frame size.

公开(公告)号：US20210342969A1

公开(公告)日：2021-11-04

申请号：US17376713

申请日：2021-07-15

Applicant: Intel Corporation

Inventor： Changliang Wang ,  Penne Lee ,  Dmitry Ermilov

IPC: G06T1/20 ,  G06T9/00 ,  G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G09G5/36

Abstract: An apparatus and method for multi-adapter and/or multi-pass encoding on dual graphics processors. For example, one embodiment of a processor comprises: a central processor integrated on a first die, the central processor comprising a plurality of cores to execute instructions and process data; an first graphics processor integrated on the first die, the first graphics processor comprising media processing circuitry to perform one or more preliminary lookahead operations on video content to generate lookahead statistics; an interconnect to couple the first graphics processor to a lookahead buffer, the first graphics processor to transmit the lookahead statistics over the interconnect to the lookahead buffer; wherein the lookahead statistics are to be used by a second graphics processor to encode the video content to generate encoded video.

公开(公告)号：US11019263B2

公开(公告)日：2021-05-25

申请号：US16847102

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Stanley J. Baran ,  Abhishek R. Appu ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Jong Dae Oh ,  Hiu-Fai R. Chan ,  Joydeep Ray ,  Barnan Das ,  Archie Sharma ,  Richmond Hicks ,  Changliang Wang ,  Satyanarayana Avadhanam ,  Robert J. Johnston ,  Narayan Biswal

IPC: H04N7/00 ,  H04N5/14 ,  H04N5/232 ,  G03B17/56 ,  G03B37/04 ,  H04N5/225 ,  G06F3/01 ,  G02B27/01 ,  H04N13/243 ,  H04N19/167 ,  H04N21/4402 ,  H04N21/442 ,  H04N21/81 ,  H04N19/17 ,  H04N21/4728 ,  H04N19/179 ,  H04N21/4223 ,  H04N21/2343 ,  H04N19/132 ,  H04N21/218 ,  H04N13/344 ,  H04N13/383 ,  H04N13/25 ,  H04N13/271 ,  H04N13/00

Abstract: Systems and methods may provide for capturing 360 degree video, and multi-resolution encoding, processing and displaying of the video based on a field of view (FOV) and region of interest (ROI) for a viewer. The ROI may be determined based on eye tracking information (ETI) and the video may be encoded for viewports within the FOV at a high resolution and for other viewports outside the FOV at a lower resolution. ROI in the video may be encoded at a high resolution and areas outside of the ROI may be encoded at a lower resolution. The ETI enables the selective display of one or more warnings based on the gaze of a user to improve the efficiency of the warning. 3D glasses having variable lens may be used to adjust the focal distance of a virtual display to match a virtual distance of an object based on stereo distance cues.

公开(公告)号：US11010861B2

公开(公告)日：2021-05-18

申请号：US16677480

申请日：2019-11-07

Applicant: Intel Corporation

Inventor： Kunjal Parikh ,  Srikanth Kambhatla ,  Gary Smith ,  Changliang Wang

IPC: G06T1/20 ,  G09G3/32 ,  G09G3/3208 ,  G06K9/00

Abstract: A smart display including one or more groups of smart pixels and at least one graphics engine. The at least one graphics engine is fragmented into GPU (graphics processing unit) minute cores. The GPU minute cores are distributed throughout the smart display. The smart pixels with distributed graphics within the smart display perform deep learning. Libraries stored on GPU minute core embedded memory are used to perform object identification using deep learning. The smart display monitors for pixel degradation and, if necessary, performs pixel enhancement.

公开(公告)号：US10908679B2

公开(公告)日：2021-02-02

申请号：US15495034

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Robert J. Johnston ,  Satyanarayana Avadhanam ,  Changliang Wang ,  Narayan Biswal ,  Archie Sharma ,  Richmond Hicks ,  Joydeep Ray ,  Abhishek R. Appu ,  Stanley J. Baran ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Jong Dae Oh ,  Hiu-Fai Chan ,  Sumit Mohan ,  Jill M. Boyce ,  Yi-Jen Chiu

IPC: G06F3/01 ,  G06T15/10

Abstract: Systems, apparatuses and methods may provide for technology to improve user experience when viewing simulated 3D objects on a display. Head and upper-body movements may be tracked and recognized as gestures to alter the displayed viewing angle. The technology provides for a very natural way to look around, under, or over objects.