-
公开(公告)号：US10276219B2
公开(公告)日：2019-04-30
申请号：US15718388
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： George Vergis , Dat Le
Abstract: In one embodiment, an apparatus comprises a first connector to couple to a connector of a memory card, the memory card comprising a first sense node to sense a supply voltage at a first location of the memory card, the first connector comprising a voltage supply pin; a ground pin; and a sense pin to couple to the first sense node; a first sense line to couple to the first sense node through the sense pin; and a voltage regulator coupled to the first sense line, the voltage regulator to provide the supply voltage based on feedback received from the first sense node of the memory card via the first sense line.
-
公开(公告)号：US20190045632A1
公开(公告)日：2019-02-07
申请号：US16051573
申请日：2018-08-01
Applicant: Intel Corporation
Inventor： Xiang Li , Jun Liao , Yunhui CHU , George Vergis , Chong Zhao
Abstract: Various aspects are related to a connector, e.g., for connecting two boards with one another. The connector may include a housing and a plurality of pins. The housing may include a first housing surface and a second housing surface opposite the first housing surface. Each pin of the plurality of pins may include a first portion protruding arcuately from the first housing surface and a second portion protruding arcuately from the second housing surface.
-
公开(公告)号：US20190042495A1
公开(公告)日：2019-02-07
申请号：US15898909
申请日：2018-02-19
Applicant: Intel Corporation
Inventor： Kenneth P. Foust , Amit Kumar Srivastava , George Vergis
Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.
-
公开(公告)号：US10146711B2
公开(公告)日：2018-12-04
申请号：US15196014
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Bill Nale , Kuljit S. Bains , George Vergis , Christopher E. Cox , James A. McCall , Chong J. Zhao , Suneeta Sah , Pete D. Vogt , John R. Goles
IPC: G06F13/16 , G11C14/00 , G11C11/4096 , G06F13/40
Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
-
公开(公告)号：US20170185486A1
公开(公告)日：2017-06-29
申请号：US14998196
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Mohan J. Kumar , George Vergis , Sarathy Jayakumar
CPC classification number: G06F3/0659 , G06F13/16 , G06F13/28 , G06F21/14 , G06F21/53 , G06F2221/2143
Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.
-
Patent Agency Ranking
公开(公告)号：US20160378623A1
公开(公告)日：2016-12-29
申请号：US14752585
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Mohan J. Kumar , Murugasamy K. Nachimuthu , George Vergis
CPC classification number: G06F11/2069 , G06F3/0619 , G06F3/0647 , G06F3/0685 , G06F11/00 , G06F11/3034 , G06F11/3058 , G06F2201/82
Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.
Abstract translation: 实施例通常涉及具有关闭设备存储的高容量能量回馈存储器。 存储器件包括电路板; 安装在电路板上的多个存储器芯片; 当检测到功率损耗状况时，控制器提供备份存储器芯片的内容; 与备用能源的连接; 以及与存储设备分离的备份数据存储器的连接。
-
公开(公告)号：US12147698B2
公开(公告)日：2024-11-19
申请号：US17214770
申请日：2021-03-26
Applicant: Intel Corporation
Inventor： Bill Nale , George Vergis
Abstract: An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.
-
公开(公告)号：US12040568B2
公开(公告)日：2024-07-16
申请号：US17128803
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Xiang Li , Konika Ganguly , George Vergis
IPC: H01R13/6461 , H01R12/70 , H01R12/71 , H01R13/24
CPC classification number: H01R12/7076 , H01R12/7082 , H01R12/714 , H01R13/2435
Abstract: Connectors with a staggered pin orientation can reduce crosstalk amongst signal pins. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. Each of the plurality of pins includes two ends including a card or module-facing end to couple with the card or module and a motherboard-facing end to couple with the motherboard. Each of the plurality of pins includes a middle section in the connector housing. One or both of the ends include one or more bends relative to the middle section. The plurality of pins includes alternating signal pins and ground pins, wherein the signal pins having an opposite orientation relative to the ground pins.
-
公开(公告)号：US11921652B2
公开(公告)日：2024-03-05
申请号：US17705439
申请日：2022-03-28
Applicant: Intel Corporation
Inventor： Kenneth P. Foust , Amit Kumar Srivastava , George Vergis
CPC classification number: G06F13/1673 , G06F12/0623 , G06F12/063 , G06F13/4027 , G06F13/4282
Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.
-
30.发明授权公开(公告)号：US11334511B2
公开(公告)日：2022-05-17
申请号：US16655511
申请日：2019-10-17
Applicant: Intel Corporation
Inventor： Rajesh Bhaskar , Enrico Carrieri , Kenneth Foust , Janusz Jurski , Myron Loewen , Matthew A. Schnoor , Amit Kumar Srivastava , George Vergis
Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.
-
-
-
-
-
-
-
-
-
Search Results
75
records
(took 0.026 seconds)
