公开(公告)号：US12020054B2

公开(公告)日：2024-06-25

申请号：US17256204

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Kun Tian ,  Ankur Shah ,  David Cowperthwaite ,  Zhi Wang ,  Zhenyu Wang ,  Kalyan Kondapally ,  Jonathan Bloomfield ,  Wei Zhang

IPC: G06F9/455 ,  G06F3/14 ,  G06F9/4401 ,  G06F9/451 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G06F9/45558 ,  G06F3/1407 ,  G06F9/4411 ,  G06F9/452 ,  G06F9/455 ,  G09G5/001 ,  G09G5/006 ,  G06F2009/45562 ,  G06F2009/45595 ,  G09G5/393 ,  G09G5/395

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

公开(公告)号：US11960422B2

公开(公告)日：2024-04-16

申请号：US17431739

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yan Zhao ,  Yu Zhang

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Systems, apparatuses and methods may provide for a frontend driver that notifies a hypervisor of a map request from a guest driver of a device, wherein the device is passed through to and directly controlled by a virtual machine, and wherein the map request is associated with an attempt of the device to access a guest memory page in a virtualized execution environment. The frontend driver may also determine whether the guest memory page is pinned and send a map hypercall to the hypervisor if the guest memory page is not pinned. Additionally, the hypervisor may determine that the guest memory page is pinned, determine, based on a direct memory access (DMA) bitmap, that an unmap request from the guest driver has been issued, and unpin the guest memory page.

公开(公告)号：US11573870B2

公开(公告)日：2023-02-07

申请号：US16211924

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Nrupal Jani ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F9/455 ,  G06F13/42 ,  G06F9/48 ,  G06F13/40 ,  G06F15/173 ,  G06F3/06 ,  G06F13/16 ,  G06F9/50 ,  G06F21/60 ,  G06F9/54

Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

公开(公告)号：US11551400B2

公开(公告)日：2023-01-10

申请号：US17072253

申请日：2020-10-16

Applicant: INTEL CORPORATION

Inventor： Prasoonkumar Surti ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Kun Tian ,  Peter L. Doyle ,  Brent E. Insko ,  Adam T. Lake

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T15/50

Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

公开(公告)号：US20220245752A1

公开(公告)日：2022-08-04

申请号：US17685445

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

公开(公告)号：US11386519B2

公开(公告)日：2022-07-12

申请号：US16791904

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yao Zu Dong ,  Zhiyuan Lv

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60 ,  G06F9/4401

Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20210271481A1

公开(公告)日：2021-09-02

申请号：US17253053

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Kun Tian ,  Sanjay Kumar ,  Ashok Raj ,  Yi Liu ,  Rajesh M. Sankaran ,  Philip R. Lantz

IPC: G06F9/34 ,  G06F9/455 ,  G06F9/38 ,  G06F13/42 ,  G06F12/1009

Abstract: Process address space identifier virtualization uses hardware paging hint. The processing device (100) comprising: a processing core (110); and a translation circuit coupled to the processing core, the translation circuit to: receive a workload instruction from a guest application being executed by the processing device, the workload instruction comprising an untranslated guest process address space identifier (gPASID), a workload for an input/output (I/O) target device, and an identifier of a submission register on the I/O target device (410), access a paging data structure (PDS) associated with the guest application to retrieve a page table entry corresponding to the gPASID and the identifier of the submission register (420), determine a value of an I/O hint bit of the page table entry corresponding to the gPASID and the identifier of the submission register (430), responsive to determining that the I/O hint bit is enabled, keep the untranslated gPASID in the workload instruction (440), and provide the workload instruction to a work queue of the I/O target device (450)

公开(公告)号：US10853118B2

公开(公告)日：2020-12-01

申请号：US16062426

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yao Zu Dong

IPC: G06F9/455 ,  G06T1/20 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method are described for pattern driven page table updates. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; a hypervisor to virtualize the GPU to share the GPU among a plurality of virtual machines (VMs); a first guest page table managed within a first VM, the first guest page table comprising a plurality of page table entries; a first shadow page table managed by the hypervisor and comprising page table entries corresponding to the page table entries of the first guest page table; and a command parser to analyze a current working set of commands submitted from the first VM to the GPU, the command parser to responsively update the first shadow page table responsive to determining a set of page table entries predicted to be used based on the analysis of the working set of commands.

公开(公告)号：US10580105B2

公开(公告)日：2020-03-03

申请号：US15570256

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Kun Tian ,  Yao Zu Dong ,  Zhiyuan Lv

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06T1/60 ,  G06F9/4401

Abstract: Systems and methods for container access to graphics processing unit (GPU) resources are disclosed herein. In some embodiments, a computing system may include a physical GPU and kernel-mode driver circuitry, to communicatively couple with the physical GPU to create a plurality of emulated GPUs and a corresponding plurality of device nodes. Each device node may be associated with a single corresponding user-side container to enable communication between the user-side container and the corresponding emulated GPU. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.