公开(公告)号：US20220011849A1

公开(公告)日：2022-01-13

申请号：US17485371

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  David J. Harriman ,  Zuoguo Wu ,  Debendra Das Sharma ,  Noam Dolev Geldbard

IPC: G06F1/3234 ,  G06F3/06 ,  G06F1/3225

Abstract: A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

公开(公告)号：US20210399982A1

公开(公告)日：2021-12-23

申请号：US17391557

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US20210034565A1

公开(公告)日：2021-02-04

申请号：US16926524

申请日：2020-07-10

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US09779053B2

公开(公告)日：2017-10-03

申请号：US14580918

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Daniel S. Froelich ,  Venkatraman Iyer ,  Michelle C. Jen ,  Rahul R. Shah ,  Eric M. Lee

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4282

Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.

公开(公告)号：US09665415B2

公开(公告)日：2017-05-30

申请号：US14866955

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Joseph Murray

IPC: G06F13/00 ,  G06F9/54 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F9/546 ,  G06F13/24 ,  G06F13/4282

Abstract: A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI3) or electrical process logic (e.g., PCIe) on the “node side” between the nodes and a pooled memory controller (or pooled storage controller), and on the “pooled side” between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.

公开(公告)号：US11789892B2

公开(公告)日：2023-10-17

申请号：US17738625

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US11726939B2

公开(公告)日：2023-08-15

申请号：US17485337

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US11327920B2

公开(公告)日：2022-05-10

申请号：US16926524

申请日：2020-07-10

Applicant: Intel Corporation

Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC: G06F13/00 ,  G06F13/42

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US20210303482A1

公开(公告)日：2021-09-30

申请号：US17170619

申请日：2021-02-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US11113196B2

公开(公告)日：2021-09-07

申请号：US16140482

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/084 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.