公开(公告)号：EP2972916A1

公开(公告)日：2016-01-20

申请号：EP14778162.9

申请日：2014-02-26

Applicant: Intel Corporation

Inventor： ROYER, JR., Robert J. ,  FANNING, Blaise ,  OOI, Eng Hun

IPC: G06F13/14 ,  G06F12/00 ,  G06F11/10

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控​​制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，并实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。