公开(公告)号：US20230099093A1

公开(公告)日：2023-03-30

申请号：US17484782

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Abhishek R. APPU

IPC: G06F9/54 ,  G06T1/20 ,  G06T1/60 ,  H04L29/06

Abstract: A graphics processing apparatus includes graphics processors connected by a network connection, where the graphics processors pass compressed data. A first graphics processor stores data blocks as compressed data in a memory. The compressed data has data blocks of variable size, where a size of a block of compressed data depends on a compression ratio of the block of compressed data. A second graphics processor also stores data blocks as compressed data. The first graphics processor concatenates a variable number of blocks of compressed data into a packet of fixed size to send to the second graphics processor. The packet has a variable number of blocks of compressed data depending on the compression ratios of the multiple blocks of compressed data.

公开(公告)号：US20220327763A1

公开(公告)日：2022-10-13

申请号：US17723772

申请日：2022-04-19

Applicant: INTEL CORPORATION

Inventor： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20220058765A1

公开(公告)日：2022-02-24

申请号：US17466591

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Eric G. LISKAY ,  Prasoonkumar SURTI ,  Sudhakar KAMMA ,  Karthik VAIDYANATHAN ,  Rajasekhar PANTANGI ,  Altug KOKER ,  Abhishek RHISHEEKESAN ,  Shashank LAKSHMINARAYANA ,  Priyanka LADDA ,  Karol A. SZERSZEN

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/38

Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.

公开(公告)号：US20190317599A1

公开(公告)日：2019-10-17

申请号：US16453189

申请日：2019-06-26

Applicant: INTEL CORPORATION

Inventor： Tomas G. AKENINE-MOLLER ,  Robert M. TOTH ,  Ingo WALD ,  Aditya S. YANAMANDRA ,  Brent E. INSKO ,  Michael APODACA ,  Prasoonkumar SURTI

IPC: G06F3/01 ,  G06T15/00 ,  G06T1/20 ,  G06T3/00 ,  G06T19/00

Abstract: A virtual reality apparatus and method are described. For example, one embodiment of an apparatus comprises: a compute cluster comprising global illumination circuitry and/or logic to perform global illumination operations on graphics data in response to execution of a virtual reality application and to responsively generate a stream of samples; a filtering/compression module to perform filtering and/or compression operations on the stream of samples to generate filtered/compressed samples; a network interface to communicatively couple the compute cluster to a network, the filtered/compressed samples to be streamed over the network; a render node to receive the filtered/compressed samples streamed over the network, the render node comprising: decompression circuitry/logic to decompress the filtered/compressed samples to generate decompressed samples; a sample buffer to store the decompressed samples; and sample insertion circuitry/logic to asynchronously insert samples into a light field rendered by a light field rendering circuit/logic.

公开(公告)号：US20250053452A1

公开(公告)日：2025-02-13

申请号：US18774583

申请日：2024-07-16

Applicant: Intel Corporation

Inventor： Pawel MAJEWSKI ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Joshua BARCZAK ,  Vasanth RANGANATHAN ,  Vikranth VEMULAPALLI

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54

Abstract: Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.

公开(公告)号：US20240233250A1

公开(公告)日：2024-07-11

申请号：US18413252

申请日：2024-01-16

Applicant: INTEL CORPORATION

Inventor： Brent E. INSKO ,  Prasoonkumar SURTI

IPC: G06T15/40 ,  G06T15/00 ,  H04N13/279 ,  H04N13/344 ,  H04N13/383 ,  H04N13/398

CPC classification number: G06T15/405 ,  G06T15/005 ,  H04N13/279 ,  H04N13/344 ,  H04N13/383 ,  H04N13/398

Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.

公开(公告)号：US20240104825A1

公开(公告)日：2024-03-28

申请号：US18376098

申请日：2023-10-03

Applicant: INTEL CORPORATION

Inventor： Karol SZERSZEN ,  Prasoonkumar SURTI ,  Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Sven WOOP

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06T15/08 ,  G06T17/10

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20240020911A1

公开(公告)日：2024-01-18

申请号：US17826090

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Michael NORRIS ,  Abhishek R. APPU ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN

IPC: G06T15/06 ,  G06T1/60

CPC classification number: G06T15/06 ,  G06T1/60

Abstract: Apparatus and method for routing data from ray tracing cache banks For example, one embodiment of an apparatus comprises: ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and an inter-bank interconnect comprising: a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks; an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

公开(公告)号：US20230096188A1

公开(公告)日：2023-03-30

申请号：US17485262

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Abhishek R. APPU ,  John H. FEIT

IPC: G06T15/00 ,  G06T1/60 ,  G06T3/00

Abstract: Examples include techniques for a fast clear of a 3-dimensional (3D) surface. Examples include re-describing 3D surface to a 2D surface using various dimension of the 3D surface as inputs in an algorithm to output a 2-dimensional (2D) surface as a re-description of the 3D surface. The algorithm to also includes additional inputs associated with a tiling mode used to read or write the 3D surface to a graphics display and a bit per pixel format to output the 2D surface. 2D surface width and height associated with the outputted 2D surface is included in a clear command to cause the 3D surface to be cleared.

公开(公告)号：US20220261075A1

公开(公告)日：2022-08-18

申请号：US17683533

申请日：2022-03-01

Applicant: Intel Corporation

Inventor： Ingo WALD ,  Brent E. INSKO ,  Prasoonkumar SURTI ,  Adam T. LAKE ,  Peter L. DOYLE ,  Daniel POHL

IPC: G06F3/01 ,  G02B27/00

Abstract: One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.