公开(公告)号：WO2013105913A2

公开(公告)日：2013-07-18

申请号：PCT/US2011/062501

申请日：2011-11-30

Applicant: INTEL CORPORATION ,  RAMADOSS, Murali ,  SAMSON, Eric

Inventor： RAMADOSS, Murali ,  SAMSON, Eric

IPC: G06F9/06 ,  G06F13/14 ,  G06T1/00

CPC classification number: G06T1/20 ,  G06F1/324 ,  G06F1/3265 ,  G06F3/14 ,  G06T1/60 ,  G09G5/18 ,  G09G2330/021 ,  G09G2340/0435 ,  Y02D10/126 ,  Y02D10/153 ,  Y02D50/20

Abstract: Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.

Abstract translation: 公开了用于基于平均帧速率与目标帧速率的比较以及还基于图形子系统是否处于图像子系统和/或处理器的性能状态来调整图形子系统和/或处理器的性能状态的示例 突发模式或持续操作模式。

公开(公告)号：WO2013100936A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067490

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  VEMBU, Balaji ,  RAMADOSS, Murali

Inventor： VEMBU, Balaji ,  RAMADOSS, Murali

IPC: G06F9/06 ,  G06F9/44 ,  G06F12/00

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0292 ,  G06F2212/205 ,  G06T1/60 ,  G11C14/0045 ,  Y02D10/13

Abstract: A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

Abstract translation: 描述了在易失性和非易失性存储器之间分发代码和数据存储的方法，设备和系统。 在一个实施例中，该方法包括将具有交换机（PCMS）设备的软件应用的一个或多个静态代码段存储在相变存储器中，将该软件应用的一个或多个静态数据段存储在PCMS设备中，并存储一个或多个 在易失性存储器件中软件应用的更易变的数据段。 该方法然后将至少一个第一地址指针的地址映射表分配给一个或多个静态代码段中的每一个，至少第二地址指针指向一个或多个静态数据段中的每一个，并且至少 指向一个或多个易失性数据段中的每一个的第三地址指针。

公开(公告)号：WO2013100935A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067489

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  VEAL, Bryan, E. ,  SCHLUESSLER, Travis, T. ,  RAMADOSS, Murali ,  VEMBU, Balaji

Inventor： VEAL, Bryan, E. ,  SCHLUESSLER, Travis, T. ,  RAMADOSS, Murali ,  VEMBU, Balaji

IPC: G06F9/06 ,  G06F9/44 ,  G06F12/00

CPC classification number: G06T1/60 ,  G11C16/349

Abstract: Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

Abstract translation: 描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。 在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。 该方法还包括执行图形应用的图形处理器。 图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。 该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

公开(公告)号：WO2013090520A1

公开(公告)日：2013-06-20

申请号：PCT/US2012/069411

申请日：2012-12-13

Applicant: INTEL CORPORATION ,  KOKER, Altug ,  SHAH, Shailesh ,  NAVALE, Aditya ,  RAMADOSS, Murali ,  DAMARAJU, Satish K.

Inventor： KOKER, Altug ,  SHAH, Shailesh ,  NAVALE, Aditya ,  RAMADOSS, Murali ,  DAMARAJU, Satish K.

IPC: G06F11/10 ,  G11C29/42

CPC classification number: G06F11/1048 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057

Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

Abstract translation: 公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。 在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。 存储结构是存储多个数据值。 奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。 错误存储空间是存储奇偶校验错误检测的指示。 错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

公开(公告)号：EP3618004A1

公开(公告)日：2020-03-04

申请号：EP19183092.6

申请日：2019-06-28

Applicant: INTEL Corporation

Inventor： SCHLUESSLER, Travis ,  WATERS, Zack ,  APODACA, Michael ,  JOHNSTON, Daniel ,  SURPRISE, Jason ,  SURTI, Prasoonkumar ,  MAIYURAN, Subramaniam ,  DOYLE, Peter ,  SHARMA, Saurabh ,  SHAH, Ankur ,  RAMADOSS, Murali

IPC: G06T15/00 ,  G06T11/40

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：EP3382652A1

公开(公告)日：2018-10-03

申请号：EP18165313.0

申请日：2018-03-30

Applicant: INTEL Corporation

Inventor： LAURITZEN, Andrew T. ,  KOKER, Altug ,  FENG, Louis ,  JANCZAK, Tomasz ,  CIMINI, David M. ,  VAIDYANATHAN, Karthik ,  VENKATESH, Abhishek ,  RAMADOSS, Murali ,  APODACA, Michael ,  SURTI, Prasoonkumar

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/30

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T15/005 ,  G06T15/06 ,  G06T15/30 ,  G06T15/80 ,  G06T17/20

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：EP3161759A1

公开(公告)日：2017-05-03

申请号：EP15812826.4

申请日：2015-06-09

Applicant: Intel Corporation

Inventor： RAMADOSS, Murali ,  PENDLURU, Nishanth R. ,  FRIZZELL, Jeffrey S. ,  SHAH, Ankur N.

IPC: G06Q10/10 ,  G06T1/00

CPC classification number: G06T1/20 ,  G06F9/5044 ,  G06F2209/509 ,  Y02D10/22

Abstract: Methods and systems may provide for receiving, at a controller, a notification of a workload submission by an application lacking system level privileges. Additionally, the controller may be used to schedule a transfer of the workload submission to a graphics hardware component for execution, wherein the controller has system level privileges. In one example, the transfer bypasses an operating system and a kernel mode driver associated with the graphics hardware component.

Abstract translation: 方法和系统可以在控制器处提供由缺乏系统级特权的应用程序接收工作负载提交的通知。 此外，控制器可用于调度工作负载提交到图形硬件组件的传送以供执行，其中控制器具有系统级权限。 在一个示例中，转移绕过与图形硬件组件相关联的操作系统和内核模式驱动程序。

公开(公告)号：EP3591519A1

公开(公告)日：2020-01-08

申请号：EP19180125.7

申请日：2019-06-13

Applicant: Intel Corporation

Inventor： APODACA, Michael ,  SHAH, Ankur ,  ASHBAUGH, Ben ,  FLIFLET, Brandon ,  NALLURI, Hema ,  K, Pattabhiraman ,  DOYLE, Peter ,  KOSTON, Joseph ,  VALERIO, James ,  RAMADOSS, Murali ,  KOKER, Altug ,  NAVALE, Aditya ,  SURTI, Prasoonkumar ,  VEMBU, Balaji

IPC: G06F9/38

Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.

公开(公告)号：EP3396633A1

公开(公告)日：2018-10-31

申请号：EP18168631.2

申请日：2018-04-20

Applicant: INTEL Corporation

Inventor： SURTI, Prasoonkumar ,  VAIDYANATHAN, Karthik ,  KUWAHARA, Atsuo ,  LABBE, Hugues ,  KP, Sameer ,  KENNEDY, Jonathan ,  APPU, Abhishek R. ,  BOLES, Jeffrey S. ,  VEMBU, Balaji ,  APODACA, Michael ,  GRAJEWSKI, Slawomir ,  LIKTOR, Gabor ,  CIMINI, David M. ,  LAURITZEN, Andrew T. ,  SCHLUESSLER, Travis T. ,  RAMADOSS, Murali ,  VENKATESH, Abhishek ,  RAY, Joydeep ,  XIAO, Kai ,  SHAH, Ankur N. ,  KOKER, Altug

IPC: G06T15/00 ,  G06T15/40

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.

公开(公告)号：EP2798455B1

公开(公告)日：2018-07-25

申请号：EP11878425.5

申请日：2011-12-30

Applicant: Intel Corporation

Inventor： KOKER, Altug ,  NAVALE, Aditya ,  VEMBU, Balaji ,  RAMADOSS, Murali

IPC: G06F9/48 ,  G06F15/167 ,  G06F12/08 ,  G06F13/10 ,  G06F9/54 ,  G06F12/14

CPC classification number: G06F9/50 ,  G06F9/4812 ,  G06F9/545 ,  G06F12/1491 ,  G06F15/167

Abstract: Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.