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    Method and apparatus for cache line write back operation
    21.
    发明授权
    Method and apparatus for cache line write back operation 有权
    高速缓存行回写操作的方法和装置

    公开(公告)号：US09471494B2

    公开(公告)日：2016-10-18

    申请号：US14137432

    申请日：2013-12-20

    Applicant: Intel Corporation

    Inventor： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032 ,  G06F2212/222

    Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

    Abstract translation: 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

    Signaling software recoverable errors
    23.
    发明授权
    Signaling software recoverable errors 有权
    信令软件可恢复的错误

    公开(公告)号：US09141454B2

    公开(公告)日：2015-09-22

    申请号：US13728217

    申请日：2012-12-27

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

    IPC: G06F11/00 ,  G06F11/07

    CPC classification number: G06F11/006 ,  G06F11/0715 ,  G06F11/0772 ,  G06F11/0793

    Abstract: Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.

    Abstract translation: 公开了用于信令软件可恢复错误的发明的实施例。 在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。 第一个单位是检测毒物的错误。 可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。 第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

    Techniques for virtual machine transfer and resource management
    25.
    发明授权
    Techniques for virtual machine transfer and resource management 有权

    公开(公告)号：US11995462B2

    公开(公告)日：2024-05-28

    申请号：US18153177

    申请日：2023-01-11

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Kun Tian ,  Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

    CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

    HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES
    29.
    发明申请
    HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES 有权

    公开(公告)号：US20230103000A1

    公开(公告)日：2023-03-30

    申请号：US17485386

    申请日：2021-09-25

    Applicant: Intel Corporation

    Inventor： Rupin Vakharwala ,  Prashant Sethi ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  David J. Harriman ,  Utkarsh Y. Kakaiya ,  Vinay Raghav ,  Ashok Raj ,  Siva Bhanu Krishna Boga

    IPC: G06F12/1027 ,  G06F12/0802 ,  G06F13/42

    Abstract: Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer. The second interconnect is in the only path between the device and the system memory.

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