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公开(公告)号：US11360914B2
公开(公告)日：2022-06-14
申请号：US17008991
申请日：2020-09-01
Applicant: Intel Corporation
Inventor： Niranjan L. Cooray , Abhishek R. Appu , Altug Koker , Joydeep Ray , Balaji Vembu , Pattabhiraman K , David Puffer , David J. Cowperthwaite , Rajesh M. Sankaran , Satyeshwar Singh , Sameer Kp , Ankur N. Shah , Kun Tian
IPC: G06F12/109 , G06F11/07 , G06F13/16 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/0802 , G06F13/40
Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
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22.发明申请公开(公告)号：US20200334896A1
公开(公告)日：2020-10-22
申请号：US16865587
申请日：2020-05-04
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
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公开(公告)号：US10769078B2
公开(公告)日：2020-09-08
申请号：US16453995
申请日：2019-06-26
Applicant: Intel Corporation
Inventor： Niranjan L. Cooray , Abhishek R. Appu , Altug Koker , Joydeep Ray , Balaji Vembu , Pattabhiraman K , David Puffer , David J. Cowperthwaite , Rajesh M. Sankaran , Satyeshwar Singh , Sameer Kp , Ankur N. Shah , Kun Tian
IPC: G06F12/109 , G06F11/07 , G06F13/16 , G06F12/1009 , G06F12/1027 , G06F12/1036 , G06F12/0802 , G06F13/40
Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
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公开(公告)号：US10649521B2
公开(公告)日：2020-05-12
申请号：US15494584
申请日：2017-04-24
Applicant: Intel Corporation
Inventor： Ravindra A. Babu , Sashank Sms Ms , Satyanantha R. Musunuri , Sagar C. Pawar , Kalyan K. Kaipa , Vijayakumar Balakrishnan , Sameer Kp
Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
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公开(公告)号：US10275924B2
公开(公告)日：2019-04-30
申请号：US14127960
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Sameer Kp , Sanjeev Tiwari
Abstract: Techniques for managing a three-dimensional (3D) graphics display mode are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics processing module, and the graphics processing module may be operative by the processor circuit to execute a graphics context in a 3D display mode if a 3D-aware graphics context data structure includes an entry corresponding to the graphics context or to execute the graphics context in a non-3D display mode if the 3D-aware graphics context data structure does not include an entry corresponding to the graphics context. Other embodiments are described and claimed.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20180293961A1
公开(公告)日：2018-10-11
申请号：US15483748
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Hugues Labbe , Karthik Vaidyanathan , Prasoonkumar Surti , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy
Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.
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公开(公告)号：US20160148596A1
公开(公告)日：2016-05-26
申请号：US14552665
申请日：2014-11-25
Applicant: Intel Corporation
Inventor： Susanta Bhattacharjee , Sameer Kp
IPC: G09G5/06
CPC classification number: G09G5/06 , G09G5/363 , G09G2340/06
Abstract: By converting a first color space to a second color space, using a two-dimensional lookup table in said second color space, and converting from said second color space to said first color space, it may be possible to use one or more two-dimensional lookup tables (LUTs) to do a task conventionally handled by three-dimensional lookup tables. This may reduce storage requirements and memory bandwidth requirements in some embodiments. In general a color pixel with N color components can be processed with n number of M dimensional LUT where M
Abstract translation: 通过将第一颜色空间转换为第二颜色空间，使用所述第二颜色空间中的二维查找表，并从所述第二颜色空间转换为所述第一颜色空间，可以使用一个或多个二维 查找表（LUT）来执行通常由三维查找表处理的任务。 这在一些实施例中可以减少存储要求和存储器带宽要求。 通常，可以用n个M维LUT来处理具有N个颜色分量的彩色像素，其中M
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公开(公告)号：US20240231478A9
公开(公告)日：2024-07-11
申请号：US18497136
申请日：2023-10-30
Applicant: Intel Corporation
Inventor： Ravindra A. Babu , Sashank Ms , Satyanantha R. Musunuri , Sagar C. Pawar , Kalyan K. Kaipa , Vijayakumar Balakrishnan , Sameer Kp
CPC classification number: G06F3/012 , G02B27/017 , G06F3/017 , G06T1/20 , G02B2027/0147 , G06F3/011
Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
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公开(公告)号：US11907416B1
公开(公告)日：2024-02-20
申请号：US18181615
申请日：2023-03-10
Applicant: Intel Corporation
Inventor： Ravindra A. Babu , Sashank Ms , Satyanantha R. Musunuri , Sagar C. Pawar , Kalyan K. Kaipa , Vijayakumar Balakrishnan , Sameer Kp
CPC classification number: G06F3/012 , G02B27/017 , G06F3/017 , G06T1/20 , G02B2027/0147 , G06F3/011
Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
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公开(公告)号：US11619987B2
公开(公告)日：2023-04-04
申请号：US16925609
申请日：2020-07-10
Applicant: Intel Corporation
Inventor： Ravindra A. Babu , Sashank Ms , Satyanantha R. Musunuri , Sagar C. Pawar , Kalyan K. Kaipa , Vijayakumar Balakrishnan , Sameer Kp
Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
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