公开(公告)号：EP1236107B1

公开(公告)日：2008-04-23

申请号：EP00970828.0

申请日：2000-10-11

Applicant: Intel Corporation

Inventor： RODGERS, Dion ,  TOLL, Bret ,  WOOD, Amiee

IPC: G06F9/46

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/384 ,  G06F9/3851 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method includes maintaining an indication of a pending event with respect to each of a number of threads supported within a multithreaded processor. An indication is also maintained of an active or inactive state for each of the multiple threads. A clock disable condition is detected. This clock disable condition may be indicated by the absence of pending events with respect to each of the multiple threads and an inactive state for each of the multiple threads. A clocks signal, if enabled, is then disabled with respect to at least one functional unit within the multithreaded processor responsive to the detection of the clock disable condition.

公开(公告)号：EP4177738A1

公开(公告)日：2023-05-10

申请号：EP22217001.1

申请日：2019-06-26

Applicant: INTEL Corporation

Inventor： TOLL, Bret ,  HUGHES, Christopher J. ,  BAUM, Dan ,  OULD-AHMED-VALL, Elmoustapha ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  HEINECKE, Alexander F.

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor comprises fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional, 2D, matrix and a one-dimensional, 1D, vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, or a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector; decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：EP3623941A3

公开(公告)日：2020-05-06

申请号：EP19183501.6

申请日：2019-06-28

Applicant: INTEL Corporation

Inventor： OULD-AHMED-VALL, Elmoustapha ,  HUGHES, Christopher J. ,  TOLL, Bret ,  BAUM, Dan ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  HEINECKE, Alexander F.

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Disclosed embodiments relate to systems and methods for performing instructions specifying ternary tile operations. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction specifying a ternary tile operation, and locations of destination and first, second, and third source matrices, each of the matrices having M rows by N columns; and execution circuitry to respond to the decoded instruction by, for each equal-sized group of K elements of the specified first, second, and third source matrices, generate K results by performing the ternary tile operation in parallel on K corresponding elements of the specified first, second, and third source matrices, and store each of the K results to a corresponding element of the specified destination matrix, wherein corresponding elements of the specified source and destination matrices occupy a same relative position within their associated matrix.

公开(公告)号：EP3629157A2

公开(公告)日：2020-04-01

申请号：EP19183061.1

申请日：2019-06-27

Applicant: INTEL Corporation

Inventor： TOLL, Bret ,  HEINECKE, Alexander F. ,  HUGHES, Christopher J. ,  ZOHAR, Ronen ,  ESPIG, Michael ,  BAUM, Dan ,  SADE, Raanan ,  VALENTINE, Robert ,  CHARNEY, Mark J. ,  OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/30 ,  G06F12/02 ,  G06F12/08 ,  G06T1/20

Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.