公开(公告)号：US11947977B2

公开(公告)日：2024-04-02

申请号：US18146289

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Li Xu ,  Haihao Xiang ,  Feng Chen ,  Travis Schluessler ,  Yuheng Zhang ,  Sen Lin

IPC: G06F9/448 ,  G06F16/215 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/4488 ,  G06F16/215 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

公开(公告)号：US20230236847A1

公开(公告)日：2023-07-27

申请号：US18146289

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Li Xu ,  Haihao Xiang ,  Feng Chen ,  Travis Schluessler ,  Yuheng Zhang ,  Sen Lin

IPC: G06F9/448 ,  G06F16/215 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F9/4488 ,  G06F16/215 ,  G06T1/60 ,  G06T1/20

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

公开(公告)号：US20230186545A1

公开(公告)日：2023-06-15

申请号：US17551647

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss ,  Rajabali Koduri

IPC: G06T15/00 ,  G06T15/20 ,  G06T1/20 ,  H04N19/597 ,  G06T15/04

CPC classification number: G06T15/005 ,  G06T15/20 ,  G06T1/20 ,  H04N19/597 ,  G06T15/04

Abstract: Described herein is a cloud-based gaming system in which multiple views of a spectated E-sports event can be rendered and combined into an immersive video having at least three degrees of freedom. Low-latency generation of the immersive video is facilitated via the use of GPU-controlled non-volatile memory on which rendered data for multiple viewpoints are stored.

公开(公告)号：US11580027B2

公开(公告)日：2023-02-14

申请号：US16802427

申请日：2020-02-26

Applicant: Intel Corporation

Inventor： Zack S. Waters ,  Travis Schluessler ,  Michael Apodaca ,  Ankur Shah

IPC: G06F12/0882 ,  G06F12/0837 ,  G06F12/1045 ,  G06F11/30 ,  G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/06

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

公开(公告)号：US20230039853A1

公开(公告)日：2023-02-09

申请号：US17968469

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06T1/60

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

公开(公告)号：US11481864B2

公开(公告)日：2022-10-25

申请号：US17234039

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06T1/60

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

公开(公告)号：US11386013B2

公开(公告)日：2022-07-12

申请号：US16902909

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Sudarshanram Shetty ,  Ping Hang Cheung ,  Aravindh Anantaraman ,  Travis Schluessler

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0893 ,  G06F9/30 ,  G06F9/50 ,  G06F11/30 ,  G06F12/0862 ,  G06F12/0873

Abstract: An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.

公开(公告)号：US11069123B2

公开(公告)日：2021-07-20

申请号：US16236218

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carson Brownlee ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Philip Laws ,  Thomas Raoux ,  Travis Schluessler

IPC: G06T15/06 ,  G06T15/00

Abstract: Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.

公开(公告)号：US20210141649A1

公开(公告)日：2021-05-13

申请号：US17090295

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Li Xu ,  Haihao Xiang ,  Feng Chen ,  Travis Schluessler ,  Yuheng Zhang ,  Sen Lin

IPC: G06F9/448 ,  G06T1/20 ,  G06T1/60 ,  G06F16/215

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

公开(公告)号：US10909741B2

公开(公告)日：2021-02-02

申请号：US16236176

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC: G06T15/06 ,  G06T15/00 ,  G06T1/60

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.