公开(公告)号：US10444817B2

公开(公告)日：2019-10-15

申请号：US15488662

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

IPC: G09G5/36 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

公开(公告)号：US10417734B2

公开(公告)日：2019-09-17

申请号：US15698217

申请日：2017-09-07

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US10324721B2

公开(公告)日：2019-06-18

申请号：US15488947

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G11C11/00 ,  G06F9/30 ,  G11C17/18 ,  G11C17/16 ,  G06F13/40 ,  G11C11/4094 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US20190109582A1

公开(公告)日：2019-04-11

申请号：US16180604

申请日：2018-11-05

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Anupama A. Thaploo ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: H03K3/012 ,  H03K3/356 ,  H03K19/21

CPC classification number: H03K3/012 ,  H03K3/356 ,  H03K3/35606 ,  H03K19/215

Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.

公开(公告)号：US20180300098A1

公开(公告)日：2018-10-18

申请号：US15489096

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  H04L29/06

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20180300074A1

公开(公告)日：2018-10-18

申请号：US15488723

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Kamal Sinha ,  Bhushan M. Borole ,  Altug Koker ,  Joydeep Ray ,  Wenyin Fu

IPC: G06F3/06 ,  G06T1/20

Abstract: Power for on-die heavily used local memories in general purpose graphics processing unit (GPGPU) applications may be reduced by using low latency read and high latency write operations. Power consumption in read heavy graphic operations can be reduced using a small memory footprint design with possible reduction of hot spotting in some embodiments.

公开(公告)号：US20180284868A1

公开(公告)日：2018-10-04

申请号：US15477029

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/32 ,  G06F3/01 ,  G06F11/30 ,  G06F11/07

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250166115A1

公开(公告)日：2025-05-22

申请号：US18971949

申请日：2024-12-06

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US12007824B2

公开(公告)日：2024-06-11

申请号：US17517090

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Bhushan M. Borole ,  Wenyin Fu ,  Kamal Sinha ,  Joydeep Ray

IPC: G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G09G5/36

CPC classification number: G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G09G5/363 ,  G09G5/366 ,  G09G2310/066 ,  G09G2310/08 ,  G09G2340/02 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2370/022 ,  G09G2370/16

Abstract: In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.

公开(公告)号：US11263720B2

公开(公告)日：2022-03-01

申请号：US16985329

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Saurabh Sharma ,  Abhishek Venkatesh ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  Altug Koker ,  Aravindh V. Anantaraman ,  Pattabhiraman P. K. ,  Abhishek R. Appu ,  Joydeep Ray ,  Kamal Sinha ,  Vasanth Ranganathan ,  Bhushan M. Borole ,  Wenyin Fu ,  Eric J. Hoekstra ,  Linda L. Hurd

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.