公开(公告)号：EP4152160A1

公开(公告)日：2023-03-22

申请号：EP22188320.0

申请日：2022-08-02

Applicant: INTEL Corporation

Inventor： WILLHALM, Thomas ,  GUIM BERNAT, Francesc ,  KUMAR, Karthik ,  GUPTA, Rita ,  SCHMISSEUR, Mark ,  ZIAKAS, Dimitrios

IPC: G06F11/14 ,  G06F21/51 ,  G06F21/57 ,  G06F11/20 ,  G06F21/60

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

公开(公告)号：EP3488352A1

公开(公告)日：2019-05-29

申请号：EP17831476.1

申请日：2017-06-14

Applicant: INTEL Corporation

Inventor： WAGH, Mahesh ,  MYERS, Mark S. ,  VAN DOREN, Stephen R. ,  ZIAKAS, Dimitrios ,  COURY, Bassam

IPC: G06F13/42

公开(公告)号：EP3712774A1

公开(公告)日：2020-09-23

申请号：EP20173833.3

申请日：2011-09-30

Applicant: INTEL Corporation

Inventor： RAMANUJAN, Raj K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille C. ,  ZIMMERMAN, David J. ,  SWAMINATHAN, Muthukumar P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan J. ,  COURY, Bassam N. ,  HINTON, Glenn J.

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/08

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."

公开(公告)号：EP2761466B1

公开(公告)日：2020-08-05

申请号：EP11873218.9

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille, C. ,  ZIMMERMAN, David, J. ,  SWAMINATHAN, Muthukumar, P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan, J. ,  COURY, Bassam N ,  HINTON, Glenn, J.

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/08

公开(公告)号：EP2761465A1

公开(公告)日：2014-08-06

申请号：EP11873192.6

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： NACHIMUTHU, Murugasamy, K. ,  KUMAR, Mohan ,  ZIAKAS, Dimitrios

IPC: G06F12/00 ,  G06F13/14 ,  G06F13/16 ,  G06F9/22

CPC classification number: G06F12/0246 ,  G06F9/4403

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM.

公开(公告)号：EP3731101A1

公开(公告)日：2020-10-28

申请号：EP20164272.5

申请日：2020-03-19

Applicant: INTEL Corporation

Inventor： BERNAT, Francesc Guim ,  ZIAKAS, Dimitrios ,  SCHMISSEUR, Mark ,  DOSHI, Kshitij ,  MALONE, Kimberly

IPC: G06F12/06 ,  G06F12/1036 ,  G06F12/02 ,  G06N3/063 ,  G06F9/50 ,  G06N3/04 ,  G06F13/16

Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.

公开(公告)号：EP3123299A1

公开(公告)日：2017-02-01

申请号：EP15769354.0

申请日：2015-01-28

Applicant: Intel Corporation

Inventor： SWANSON, Robert C. ,  TRAW, C. Brendan ,  ZIMMER, Vincent J. ,  BULUSU, Mallik ,  LINDSLEY, John R. ,  NATU, Mahesh S. ,  ZIAKAS, Dimitrios ,  CONE, Robert W. ,  RANGARAJAN, Madhusudhan ,  NIKJOU, Babak ,  BRANNOCK, Kirk D. ,  WUNDERLICH, Russell J. ,  SCHWARTZ, Miles F. ,  PAWLOWSKI, Stephen S.

IPC: G06F9/22 ,  G06F11/30

CPC classification number: G06F11/3476 ,  G06F9/4403 ,  G06F9/4416 ,  G06F11/1417 ,  G06F21/575 ,  G06F2201/84

Abstract: Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

Abstract translation: 平台控制器，计算机可读存储介质以及与计算设备的初始化相关联的方法。 在实施例中，平台控制器可以包括引导控制器和与引导控制器耦合的一个或多个非易失性存储器模块。 在实施例中，一个或多个非易失性存储器模块可以具有存储在其上的第一指令和第二指令。 第一指令可以在由托管平台控制器的计算设备的处理器执行时引起计算设备的初始化。 该第二指令，当由所述引导控制器执行时，可能会导致引导控制器以监测至少由所述计算设备的所述第一指令的执行的一部分，并且可以产生的所述第一指令的执行的所监控的部分的轨迹。 在实施例中，迹线可以被存储在一个或多个非易失性存储器模块中。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP3074878A1

公开(公告)日：2016-10-05

申请号：EP13898057.8

申请日：2013-11-27

Applicant: Intel Corporation

Inventor： ZIAKAS, Dimitrios ,  COURY, Bassam N. ,  KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  DANG, Thi ,  WUNDERLICH, Russell J.

IPC: G06F15/76

CPC classification number: G06F15/7803 ,  G06F11/1662 ,  G06F2201/805

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Abstract translation: 系统和实施服务器架构的方法都可以方便记忆组件的计算机系统中的服务。 该系统和方法采用的非易失性存储器/存储模块确实包括非易失性存储器（NVM）那样，可用于系统存储器和大容量存储器，以及固件存储器。 所述respectivement NVM /存储设备模块可在计算机系统中的正面或背面装载托架被接收。 该系统和方法进一步采用单，双，或四插口处理器，其中每个处理器可通信地耦合到至少一些由一个或多个存储器和/或输入在前面或后面装载托架设置在NVM /存储模块的 /输出（I / O）信道。 通过采用NVM /存储模块可以接收在前面或计算机系统的后部装载托架那样，该系统和方法提供了存储器组件可维护性在计算机系统中实现常规的服务器架构迄今为止不可实现的。

公开(公告)号：EP2761479A1

公开(公告)日：2014-08-06

申请号：EP11873140.5

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： ZIAKAS, Dimitrios ,  CAI, Zhong-Ning, George

IPC: G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4027 ,  G06F13/385

Abstract: A mechanism is described for facilitating customization of multipurpose interconnect agents at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes enhancing a multipurpose interconnect agent by associating a customization block to the multipurpose interconnect agent at a computing system. Enhancing may include customization of one or more functionalities of the multipurpose interconnect agent. The method may further include customizing, via the customization block, the one or more functionalities of the enhanced multipurpose interconnect agent, wherein customizing includes enabling integration of two or more processor interconnects carrying data packets.

公开(公告)号：EP2761466A1

公开(公告)日：2014-08-06

申请号：EP11873218.9

申请日：2011-09-30

Applicant: Intel Corporation

Inventor： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille, C. ,  ZIMMERMAN, David, J. ,  SWAMINATHAN, Muthukumar, P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan, J. ,  COURY, Bassam N ,  HINTON, Glenn, J.

IPC: G06F12/00 ,  G11C7/10

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”