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公开(公告)号：US20220075680A1
公开(公告)日：2022-03-10
申请号：US17530879
申请日：2021-11-19
Applicant: Infineon Technologies AG
Inventor： Thomas Zettler , Dirk Hammerschmidt , Friedrich Rasbornig , Michael Strasser , Akos Hegedus , Wolfgang Granig
Abstract: A fault detection system includes a sensor configured to measure a physical quantity and generate a measurement of the physical quantity; a first processor configured to receive the measurement, execute a first firmware based on the measurement, and output a first result of the executed first firmware; a second processor configured to receive the measurement from the sensor, execute a second firmware based on the measurement, and output a second result of the executed second firmware, wherein the first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin; and a fault detection circuit configured to detect a fault when the first result and the second result are not within the predetermined margin.
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公开(公告)号：US10756857B2
公开(公告)日：2020-08-25
申请号：US13750444
申请日：2013-01-25
Applicant: Infineon Technologies AG
Inventor： Friedrich Rasbornig , Wolfgang Granig , Bernhard Schaffer , Wolfgang Scherr , Michael Strasser
Abstract: Embodiments relate to a controller operable to transmit digital data messages to a receiver via a communication link having at least a first and a second transmission path, the controller comprising a first signal terminal the first transmission path and a second signal terminal for the second transmission path. The first signal terminal is operable to digitally transmit a first message to the receiver according to a first transmission technique and the second signal terminal is being operable to digitally transmit a second message to the receiver according to a second, different transmission technique.
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公开(公告)号：US09455849B2
公开(公告)日：2016-09-27
申请号：US14934729
申请日：2015-11-06
Applicant: Infineon Technologies AG
Inventor： Wolfgang Scherr , Christian Reidl , Michael Strasser , Veikko Summa
CPC classification number: H04L25/4902
Abstract: Methods, devices and systems are disclosed where to generate a pulse a data line is actively driven to a first voltage followed by actively driving the data line to a second voltage.
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公开(公告)号：US20150270994A1
公开(公告)日：2015-09-24
申请号：US14318741
申请日：2014-06-30
Applicant: Infineon Technologies AG
Inventor： Wolfgang Scherr , Christian Reidl , Michael Strasser , Veikko Summa
IPC: H04L25/49
CPC classification number: H04L25/4902
Abstract: Methods, devices and systems are disclosed where to generate a pulse a data line is actively driven to a first voltage followed by actively driving the data line to a second voltage.
Abstract translation: 公开了方法，装置和系统在哪里产生脉冲，数据线被主动地驱动到第一电压，随后主动地将数据线驱动到第二电压。
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公开(公告)号：US20150269019A1
公开(公告)日：2015-09-24
申请号：US14317661
申请日：2014-06-27
Applicant: Infineon Technologies AG
Inventor： Wolfgang Scherr , Christian Reidl , Michael Strasser , Veikko Summa
CPC classification number: H04L1/0061 , H03M13/09 , H04L1/0046 , H04L1/24
Abstract: Methods and devices are provided wherein feedback is included in a checksum.
Abstract translation: 提供了方法和设备，其中反馈被包括在校验和中。
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Patent Agency Ranking
公开(公告)号：US11188410B2
公开(公告)日：2021-11-30
申请号：US16809988
申请日：2020-03-05
Applicant: Infineon Technologies AG
Inventor： Thomas Zettler , Dirk Hammerschmidt , Friedrich Rasbornig , Michael Strasser , Akos Hegedus , Wolfgang Granig
IPC: G06F11/00 , G06F11/07 , G01R33/09 , G06F11/16 , G01K7/00 , G01L1/00 , G01P3/00 , G01P15/00 , G01R33/00 , G01P21/00
Abstract: Fault detection devices, systems, and methods are provided which implement identical processors. A first processor is configured to receive a first measurement, execute a first firmware based on the first measurement, and output a first result of the executed first firmware. A second processor is configured to receive a second measurement, execute a second firmware based on the second measurement, and output a second result of the executed second firmware. The first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin.
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公开(公告)号：US10606686B2
公开(公告)日：2020-03-31
申请号：US16032609
申请日：2018-07-11
Applicant: Infineon Technologies AG
Inventor： Thomas Zettler , Dirk Hammerschmidt , Friedrich Rasbornig , Michael Strasser , Akos Hegedus , Wolfgang Granig
IPC: G06F11/00 , G06F11/07 , G01R33/09 , G06F11/16 , G01K7/00 , G01L1/00 , G01P3/00 , G01P15/00 , G01R33/00 , G01P21/00
Abstract: Fault detection devices, systems and methods are provided which implement identical processors. A first processor is configured to receive a first set of variables, execute a first firmware based on the first set of variables, and output a first result of the executed first firmware. A second processor, identical to the first processor, is configured to receive a second set of variables, execute a second firmware based on the second set of variables, and output a second result of the executed second firmware. The first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin. Thus, a fault can be detected by comparing the first and the second results.
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28.发明授权公开(公告)号：US10352812B2
公开(公告)日：2019-07-16
申请号：US15130114
申请日：2016-04-15
Applicant: Infineon Technologies AG
Inventor： Dirk Hammerschmidt , Friedrich Rasbornig , Michael Strasser
Abstract: A circuit, a method, and a computer program configured to detect mechanical stress and a circuit, a method, and a computer program configured to monitor safety of a system is disclosed. The detection circuit is configured to monitor a mechanical stress level of a semiconductor circuit. The detection circuit includes a stress monitor circuit configured to monitor a signal comprising mechanical stress level information of the semiconductor circuit, a reference circuit to generate a reference signal, and a calibration circuit configured to modify at least one of the stress signal or the reference signal based on calibration information for the semiconductor circuit to obtain a at least one modified signal. The detection circuit further includes an activation signal generator configured to generate an activation signal including activation information related to the mechanical stress level of the semiconductor circuit depending on a relation between the modified signal, and the stress signal or the reference signal.
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公开(公告)号：US20190199451A1
公开(公告)日：2019-06-27
申请号：US15850683
申请日：2017-12-21
Applicant: Infineon Technologies AG
Inventor： Christoph Krall , Dirk Hammerschmidt , Michael Strasser
CPC classification number: H04B14/026 , H04L25/4902
Abstract: A sensor system with a sensor device communicatively coupled to a sensor bus to a receiver circuitry or processing component increases the data rate of sensor transmissions based on the sensor communication protocol. The sensor device can be a short pulse width modulation (PWM) code (SPC) protocol or a single edge nibble transmission (SENT) protocol. A first plurality of sensor values can be configured based on a first communication scheme and a second plurality of sensor values based on a second communication scheme of the communication protocol within a sensor transmission. An indication of modifications of the sensor communication protocol can further be provided via the transmission to sensor bus and processed accordingly by the receiver or processing circuitry of the sensor bus.
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公开(公告)号：US10187099B2
公开(公告)日：2019-01-22
申请号：US15057737
申请日：2016-03-01
Applicant: Infineon Technologies AG
Inventor： Friedrich Rasbornig , Wolfgang Granig , Bernhard Schaffer , Wolfgang Scherr , Michael Strasser
Abstract: Embodiments relate to a controller operable to transmit digital data messages to a receiver via a communication link having at least a first and a second transmission path, the controller comprising a first signal terminal the first transmission path and a second signal terminal for the second transmission path. The first signal terminal is operable to digitally transmit a first message to the receiver according to a first transmission technique and the second signal terminal is being operable to digitally transmit a second message to the receiver according to a second, different transmission technique.
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