公开(公告)号：US20220199519A1

公开(公告)日：2022-06-23

申请号：US17129854

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Ashish Verma PENUMATCHA ,  Anandi ROY

IPC: H01L23/522 ,  H01L49/02

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate.

公开(公告)号：US20220140230A1

公开(公告)日：2022-05-05

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20200161535A1

公开(公告)日：2020-05-21

申请号：US16193599

申请日：2018-11-16

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Dmitri NIKONOV ,  Ian YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.

公开(公告)号：US20200083427A1

公开(公告)日：2020-03-12

申请号：US16128426

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20190259935A1

公开(公告)日：2019-08-22

申请号：US16346872

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jasmeet S. CHAWLA ,  Sasikanth MANIPATRUNI ,  Robert L. BRISTOL ,  Chia-Ching LIN ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.

公开(公告)号：US20250113547A1

公开(公告)日：2025-04-03

申请号：US18375064

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tao CHU ,  Chiao-Ti HUANG ,  Guowei XU ,  Robin CHAO ,  Feng ZHANG ,  Yue ZHONG ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Kevin P. O’BRIEN ,  Uygar E. AVCI ,  Carl H. NAYLOR ,  Mahmut Sami KAVRIK ,  Andrey VYATSKIKH ,  Rachel STEINHARDT ,  Chelsey DOROW ,  Kirby MAXEY

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.

公开(公告)号：US20250112120A1

公开(公告)日：2025-04-03

申请号：US18375084

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Tao CHU ,  Minwoo JANG ,  Yanbin LUO ,  Paul PACKAN ,  Conor P. PULS ,  Guowei XU ,  Chiao-Ti HUANG ,  Robin CHAO ,  Feng ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Yang ZHANG ,  Chung-Hsun LIN ,  Anand S. MURTHY

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

公开(公告)号：US20250098260A1

公开(公告)日：2025-03-20

申请号：US18370287

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Guowei XU ,  Feng ZHANG ,  Chiao-Ti HUANG ,  Robin CHAO ,  Tao CHU ,  Chung-Hsun LIN ,  Oleg GOLONZKA ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Chia-Ching LIN ,  Anand S. MURTHY

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775

Abstract: Integrated circuit structures having patch spacers, and methods of fabricating integrated circuit structures having patch spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent ones of the stack of horizontal nanowires and laterally adjacent to the gate structure. An external gate spacer is along sides of the gate structure and over the stack of horizontal nanowires, the external gate spacer having one or more patch spacers therein.

公开(公告)号：US20230087624A1

公开(公告)日：2023-03-23

申请号：US17483795

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  I-Cheng TUNG ,  Chia-Ching LIN ,  Sou-Chi CHANG ,  Matthew V. METZ ,  Uygar E. AVCI ,  Arnab SEN GUPTA

IPC: H01L49/02

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199799A1

公开(公告)日：2022-06-23

申请号：US17131706

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Chelsey DOROW ,  Carl NAYLOR ,  Kirby MAXEY ,  Tanay GOSAVI ,  Uygar E. AVCI ,  Ashish Verma PENUMATCHA ,  Chia-Ching LIN ,  Shriram SHIVARAMAN ,  Sudarat LEE

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66

Abstract: Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both.