公开(公告)号：US20210294560A1

公开(公告)日：2021-09-23

申请号：US17162864

申请日：2021-01-29

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  H04L29/06 ,  G06F3/147 ,  G06T1/20 ,  G09G5/36

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20210264558A1

公开(公告)日：2021-08-26

申请号：US17135319

申请日：2020-12-28

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  David M. Cimini ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/50 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide a way to monitor, by a process monitor, one or more processing factors of one or more client devices hosting one or more user sessions. More particularly, the systems, apparatuses and methods may provide a way to generate, responsively, a scene generation plan based on one or more of a digital representation of an N dimensional space or at least one of the one or more processing factors, and generate, by a global scene generator, a global scene common to the one or more client devices based on the digital representation of the space. The systems, apparatuses and methods may further provide for performing, by a local scene generator, at least a portion of the global illumination based on one or more of the scene generation plan, or application parameters.

公开(公告)号：US11062506B2

公开(公告)日：2021-07-13

申请号：US16916875

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US11049214B2

公开(公告)日：2021-06-29

申请号：US16729767

申请日：2019-12-30

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini

IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60 ,  G06F9/50

Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.

公开(公告)号：US10896657B2

公开(公告)日：2021-01-19

申请号：US15488561

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Devan Burke ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek R. Appu

IPC: G09G5/00 ,  G09G5/391 ,  G09G5/38 ,  G06T1/20 ,  G09G5/36

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

公开(公告)号：US10706612B2

公开(公告)日：2020-07-07

申请号：US15477015

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20 ,  G06T15/30

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20200097243A1

公开(公告)日：2020-03-26

申请号：US16586043

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  G06F3/147 ,  G06T1/20 ,  G09G5/36 ,  H04L29/06

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20180308199A1

公开(公告)日：2018-10-25

申请号：US15494612

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  David M. Cimini ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/50

CPC classification number: G06T1/20 ,  G06F9/5072 ,  G06T15/005 ,  G06T15/506 ,  G06T2210/52 ,  G06T2210/61

Abstract: Systems, apparatuses and methods may provide a way to monitor, by a process monitor, one or more processing factors of one or more client devices hosting one or more user sessions. More particularly, the systems, apparatuses and methods may provide a way to generate, responsively, a scene generation plan based on one or more of a digital representation of an N dimensional space or at least one of the one or more processing factors, and generate, by a global scene generator, a global scene common to the one or more client devices based on the digital representation of the space. The systems, apparatuses and methods may further provide for performing, by a local scene generator, at least a portion of the global illumination based on one or more of the scene generation plan, or application parameters.

公开(公告)号：US20180286112A1

公开(公告)日：2018-10-04

申请号：US15477015

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T15/005 ,  G06T15/06 ,  G06T15/30 ,  G06T15/80 ,  G06T17/20

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US11948017B2

公开(公告)日：2024-04-02

申请号：US16896031

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Michael Apodaca ,  Stav Gurtovoy ,  John H. Feit ,  Mateusz Przybylski ,  David M. Cimini

IPC: G06F9/44 ,  G06F9/54 ,  G06T1/20

CPC classification number: G06F9/542 ,  G06F9/546 ,  G06T1/20

Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device; and a central processing unit (CPU). In some examples, the CPU is configured to: execute a producer to issue graphics command application program interfaces (APIs); execute a driver to translate graphics command APIs into executable instructions; and based on an idle state of the producer, execute a command translation code segment of the producer to translate graphics command APIs into executable instructions. In some examples, the execution unit is coupled to the memory device, the execution unit to execute one or more of the executable instructions. In some examples, the producer includes multiple portions such as application code, graphics pipeline runtime code, and command translation code segment.