公开(公告)号：US20190156533A1

公开(公告)日：2019-05-23

申请号：US15818607

申请日：2017-11-20

Applicant: Intel Corporation

Inventor： Devan Burke

IPC: G06T11/40 ,  G06T15/80 ,  G06T1/20

Abstract: Embodiments are generally directed to minimum or maximum sample indexing in a control surface. An embodiment of an apparatus includes a graphics processor including: a sampler to sample a value; one or more of a color unit or a depth unit; and at least one minimum or maximum sample (min/max) setter subunit for the color unit or depth unit, the min/max setter subunit to receive a new sample value, store the sample value in a resource containing a plurality of sample values, and update indexing include index values for one or more of a minimum sample value and a maximum sample value in the plurality of sample values of the resource.

公开(公告)号：US20190096117A1

公开(公告)日：2019-03-28

申请号：US15719381

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC: G06T15/04 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T15/04 ,  G06T15/005 ,  G06T15/80

Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.

公开(公告)号：US10242496B2

公开(公告)日：2019-03-26

申请号：US15494696

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Peter L. Doyle ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Philip R. Laws ,  Altug Koker

IPC: G06T15/00 ,  G06T17/20 ,  G06T15/80 ,  G06T15/04 ,  G06T17/10

Abstract: Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.

公开(公告)号：US20180308208A1

公开(公告)日：2018-10-25

申请号：US15819093

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T1/60 ,  G06F17/16

CPC classification number: G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F17/16 ,  G06F2009/45583 ,  G06T1/60

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type

公开(公告)号：US20180300933A1

公开(公告)日：2018-10-18

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US12198221B2

公开(公告)日：2025-01-14

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US20240086138A1

公开(公告)日：2024-03-14

申请号：US18474361

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Sanjeev S. Jahagirdar ,  Balaji Vembu ,  Devan Burke ,  Philip R. Laws ,  Kamal Sinha ,  Abhishek R. Appu ,  Elmoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Altug Koker

IPC: G06F3/14 ,  G06F3/01 ,  G06F3/0484 ,  G09G5/391

CPC classification number: G06F3/1438 ,  G06F3/013 ,  G06F3/0484 ,  G09G5/391 ,  G09G5/001 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/121

Abstract: In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

公开(公告)号：US11514721B2

公开(公告)日：2022-11-29

申请号：US17221283

申请日：2021-04-02

Applicant: Intel Corporation

Inventor： Radhakrishnan Venkataraman ,  James M. Holland ,  Sayan Lahiri ,  Pattabhiraman K ,  Kamal Sinha ,  Chandrasekaran Sakthivel ,  Daniel Pohl ,  Vivek Tiwari ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Devan Burke

IPC: G06V40/18 ,  G09G5/10 ,  G09G5/391 ,  G06F3/01 ,  G06F3/147 ,  G09G5/00 ,  G09G5/393 ,  G09G5/36

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

公开(公告)号：US20220262059A1

公开(公告)日：2022-08-18

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US11348198B2

公开(公告)日：2022-05-31

申请号：US17145885

申请日：2021-01-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F8/41

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.